diff --git a/boards/nucleo-l412kb/Makefile b/boards/nucleo-l412kb/Makefile new file mode 100644 index 0000000000..692b8a7fbb --- /dev/null +++ b/boards/nucleo-l412kb/Makefile @@ -0,0 +1,5 @@ +MODULE = board + +DIRS = $(RIOTBOARD)/common/nucleo + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nucleo-l412kb/Makefile.dep b/boards/nucleo-l412kb/Makefile.dep new file mode 100644 index 0000000000..7294858272 --- /dev/null +++ b/boards/nucleo-l412kb/Makefile.dep @@ -0,0 +1 @@ +include $(RIOTBOARD)/common/nucleo/Makefile.dep diff --git a/boards/nucleo-l412kb/Makefile.features b/boards/nucleo-l412kb/Makefile.features new file mode 100644 index 0000000000..88de67ae54 --- /dev/null +++ b/boards/nucleo-l412kb/Makefile.features @@ -0,0 +1,19 @@ +CPU = stm32l4 +CPU_MODEL = stm32l412kb + +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_pwm +FEATURES_PROVIDED += periph_rtt +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# Put other features for this board (in alphabetical order) +# Note that a recent version of OpenOCD with a slightly patched code is required +# for flashing this board. Refer to the following PR for more info: +# https://github.com/RIOT-OS/RIOT/pull/12144#issuecomment-527090161 +FEATURES_PROVIDED += riotboot + +# load the common Makefile.features for Nucleo-32 boards +include $(RIOTBOARD)/common/nucleo32/Makefile.features diff --git a/boards/nucleo-l412kb/Makefile.include b/boards/nucleo-l412kb/Makefile.include new file mode 100644 index 0000000000..f7dfb1e2a1 --- /dev/null +++ b/boards/nucleo-l412kb/Makefile.include @@ -0,0 +1,2 @@ +# load the common Makefile.include for Nucleo-32 boards +include $(RIOTBOARD)/common/nucleo32/Makefile.include diff --git a/boards/nucleo-l412kb/doc.txt b/boards/nucleo-l412kb/doc.txt new file mode 100644 index 0000000000..dad933a818 --- /dev/null +++ b/boards/nucleo-l412kb/doc.txt @@ -0,0 +1,5 @@ +/** +@defgroup boards_nucleo-l412kb STM32 Nucleo-L412KB +@ingroup boards_common_nucleo32 +@brief Support for the STM32 Nucleo-L412KB + */ diff --git a/boards/nucleo-l412kb/include/periph_conf.h b/boards/nucleo-l412kb/include/periph_conf.h new file mode 100644 index 0000000000..a8d3759112 --- /dev/null +++ b/boards/nucleo-l412kb/include/periph_conf.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2019 twostairs + * 2017 Inria + * 2017 OTA keys + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nucleo-l412kb + * @{ + * + * @file + * @brief Peripheral MCU configuration for the nucleo-l412kb board + * + * @author Marius + * @author Alexandre Abadie + * @author Vincent Dupont + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "periph_cpu.h" +#include "cfg_i2c1_pb6_pb7.h" +#include "cfg_timer_tim2.h" +#include "cfg_rtt_default.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock system configuration + * @{ + */ +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#define CLOCK_HSE (0) +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#define CLOCK_LSE (1) +/* 0: enable MSI only if HSE isn't available + * 1: always enable MSI (e.g. if USB or RNG is used)*/ +#define CLOCK_MSI_ENABLE (1) +/* 0: disable Hardware auto calibration with LSE + * 1: enable Hardware auto calibration with LSE (PLL-mode)*/ +#define CLOCK_MSI_LSE_PLL (1) +/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ +#define CLOCK_CORECLOCK (80000000U) +/* PLL configuration: make sure your values are legit! + * + * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) + * with: + * PLL_IN: input clock, HSE or MSI @ 48MHz + * M: pre-divider, allowed range: [1:8] + * N: multiplier, allowed range: [8:86] + * R: post-divider, allowed range: [2,4,6,8] + * + * Also the following constraints need to be met: + * (PLL_IN / M) -> [4MHz:16MHz] + * (PLL_IN / M) * N -> [64MHz:344MHz] + * CORECLOCK -> 80MHz MAX! + */ +#define CLOCK_PLL_M (6) +#define CLOCK_PLL_N (20) +#define CLOCK_PLL_R (2) +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 +#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 +#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) +/** @} */ + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = USART2, + .rcc_mask = RCC_APB1ENR1_USART2EN, + .rx_pin = GPIO_PIN(PORT_A, 15), + .tx_pin = GPIO_PIN(PORT_A, 2), + .rx_af = GPIO_AF3, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART2_IRQn, + .type = STM32_USART, + .clk_src = 0, /* Use APB clock */ + }, + { + .dev = USART1, + .rcc_mask = RCC_APB2ENR_USART1EN, + .rx_pin = GPIO_PIN(PORT_A, 10), + .tx_pin = GPIO_PIN(PORT_A, 9), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB2, + .irqn = USART1_IRQn, + .type = STM32_USART, + .clk_src = 0, /* Use APB clock */ + }, +}; + +#define UART_0_ISR (isr_usart2) +#define UART_1_ISR (isr_usart1) + +#define UART_NUMOF ARRAY_SIZE(uart_config) +/** @} */ + +/** + * @name PWM configuration + * @{ + */ +static const pwm_conf_t pwm_config[] = { + { + .dev = TIM1, + .rcc_mask = RCC_APB2ENR_TIM1EN, + .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 }, + { .pin = GPIO_UNDEF, .cc_chan = 0 }, + { .pin = GPIO_UNDEF, .cc_chan = 0 }, + { .pin = GPIO_UNDEF, .cc_chan = 0 } }, + .af = GPIO_AF1, + .bus = APB2 + } +}; + +#define PWM_NUMOF ARRAY_SIZE(pwm_config) +/** @} */ + +/** + * @name SPI configuration + * + * @note The spi_divtable is auto-generated from + * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` + * @{ + */ +static const uint8_t spi_divtable[2][5] = { + { /* for APB1 @ 20000000Hz */ + 7, /* -> 78125Hz */ + 5, /* -> 312500Hz */ + 3, /* -> 1250000Hz */ + 1, /* -> 5000000Hz */ + 0 /* -> 10000000Hz */ + }, + { /* for APB2 @ 40000000Hz */ + 7, /* -> 156250Hz */ + 6, /* -> 312500Hz */ + 4, /* -> 1250000Hz */ + 2, /* -> 5000000Hz */ + 1 /* -> 10000000Hz */ + } +}; + +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_B, 5), + .miso_pin = GPIO_PIN(PORT_B, 4), + .sclk_pin = GPIO_PIN(PORT_B, 3), + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2 + } +}; + +#define SPI_NUMOF ARRAY_SIZE(spi_config) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */