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mtd_spi_nor: MTD interface driver for SPI NOR flash memory
This is a generic SPI NOR flash driver which can be used with many different flash chips.
This commit is contained in:
Joakim Nohlgård
Vincent Dupont
parent
76bae4b111
commit
9313d8ec67
@ -218,3 +218,8 @@ endif
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ifneq (,$(filter feetech,$(USEMODULE)))
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USEMODULE += uart_half_duplex
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endif
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ifneq (,$(filter mtd_spi_nor,$(USEMODULE)))
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USEMODULE += mtd
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FEATURES_REQUIRED += periph_spi
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endif
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148
drivers/include/mtd_spi_nor.h
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148
drivers/include/mtd_spi_nor.h
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@ -0,0 +1,148 @@
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/*
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* Copyright (C) 2016 Eistec AB
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup drivers_mtd_spi_nor Serial NOR flash
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* @ingroup drivers_storage
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* @brief Driver for serial NOR flash memory technology devices attached via SPI
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*
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* @{
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*
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* @file
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* @brief Interface definition for the serial flash memory driver
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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* @author Vincent Dupont <vincent@otakeys.com>
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*/
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#ifndef MTD_SPI_NOR_H_
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#define MTD_SPI_NOR_H_
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#include <stdint.h>
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#include "periph_conf.h"
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#include "periph/spi.h"
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#include "periph/gpio.h"
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#include "mtd.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @brief SPI NOR flash opcode table
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*/
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typedef struct {
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uint8_t rdid; /**< Read identification (JEDEC ID) */
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uint8_t wren; /**< Write enable */
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uint8_t rdsr; /**< Read status register */
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uint8_t wrsr; /**< Write status register */
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uint8_t read; /**< Read data bytes, 3 byte address */
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uint8_t read_fast; /**< Read data bytes, 3 byte address, at higher speed */
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uint8_t page_program; /**< Page program */
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uint8_t sector_erase; /**< Block erase 4 KiB */
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uint8_t block_erase_32k; /**< 32KiB block erase */
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uint8_t block_erase; /**< Block erase (usually 64 KiB) */
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uint8_t chip_erase; /**< Chip erase */
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uint8_t sleep; /**< Deep power down */
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uint8_t wake; /**< Release from deep power down */
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/* TODO: enter 4 byte address mode for large memories */
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} mtd_spi_nor_opcode_t;
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/**
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* @brief Internal representation of JEDEC memory ID codes.
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*
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* @see http://www.jedec.org/standards-documents/results/jep106
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*/
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typedef struct __attribute__((packed)) {
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uint8_t bank; /**< Manufacturer ID bank number, 1 through 10, see JEP106 */
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uint8_t manuf; /**< Manufacturer ID, 1 byte */
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uint8_t device[2]; /**< Device ID, 2 bytes */
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} mtd_jedec_id_t;
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/**
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* @brief Byte to signal increment bank number when reading manufacturer ID
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*
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* @see http://www.jedec.org/standards-documents/results/jep106
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*/
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#define JEDEC_NEXT_BANK (0x7f)
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/**
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* @brief Flag to set when the device support 4KiB sector erase (sector_erase opcode)
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*/
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#define SPI_NOR_F_SECT_4K (1)
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/**
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* @brief Flag to set when the device support 32KiB block erase (block_erase_32k opcode)
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*/
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#define SPI_NOR_F_SECT_32K (2)
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/**
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* @brief Device descriptor for serial flash memory devices
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*
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* This is an extension of the @c mtd_dev_t struct
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*/
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typedef struct {
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mtd_dev_t base; /**< inherit from mtd_dev_t object */
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const mtd_spi_nor_opcode_t *opcode; /**< Opcode table for the device */
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spi_t spi; /**< SPI bus the device is connected to */
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gpio_t cs; /**< CS pin GPIO handle */
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spi_mode_t mode; /**< SPI mode */
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spi_clk_t clk; /**< SPI clock */
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uint16_t flag; /**< Config flags */
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mtd_jedec_id_t jedec_id; /**< JEDEC ID of the chip */
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/**
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* @brief bitmask to corresponding to the page address
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*
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* Computed by mtd_spi_nor_init, no need to touch outside the driver.
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*/
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uint32_t page_addr_mask;
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/**
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* @brief bitmask to corresponding to the sector address
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*
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* Computed by mtd_spi_nor_init, no need to touch outside the driver.
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*/
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uint32_t sec_addr_mask;
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uint8_t addr_width; /**< Number of bytes in addresses, usually 3 for small devices */
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/**
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* @brief number of right shifts to get the address to the start of the page
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*
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* Computed by mtd_spi_nor_init, no need to touch outside the driver.
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*/
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uint8_t page_addr_shift;
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/**
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* @brief number of right shifts to get the address to the start of the sector
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*
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* Computed by mtd_spi_nor_init, no need to touch outside the driver.
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*/
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uint8_t sec_addr_shift;
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} mtd_spi_nor_t;
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/**
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* @brief NOR flash SPI MTD device operations table
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*/
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extern const mtd_desc_t mtd_spi_nor_driver;
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/* Available opcode tables for known devices */
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/* Defined in mtd_spi_nor_configs.c */
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/**
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* @brief Default command opcodes
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*
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* The numbers were taken from Micron M25P16, but the same opcodes can
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* be found in Macronix MX25L25735E, and multiple other data sheets for
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* different devices, as well as in the Linux kernel, so they seem quite
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* sensible for default values. */
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extern const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default;
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#ifdef __cplusplus
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}
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#endif
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#endif /* MTD_SPI_NOR_H_ */
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/** @} */
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1
drivers/mtd_spi_nor/Makefile
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1
drivers/mtd_spi_nor/Makefile
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@ -0,0 +1 @@
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include $(RIOTBASE)/Makefile.base
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505
drivers/mtd_spi_nor/mtd_spi_nor.c
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505
drivers/mtd_spi_nor/mtd_spi_nor.c
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@ -0,0 +1,505 @@
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/*
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* Copyright (C) 2016 Eistec AB
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*
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*/
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/**
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* @ingroup drivers_mtd_spi_nor
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* @{
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*
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* @file
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* @brief Driver for serial flash memory attached to SPI
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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* @author Vincent Dupont <vincent@otakeys.com>
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*
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* @}
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*/
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#include <stdint.h>
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#include <errno.h>
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#include "mtd.h"
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#if MODULE_XTIMER
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#include "xtimer.h"
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#include "timex.h"
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#else
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#include "thread.h"
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#endif
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#include "byteorder.h"
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#include "mtd_spi_nor.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#define ENABLE_TRACE (0)
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#if ENABLE_TRACE
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#define TRACE(...) DEBUG(__VA_ARGS__)
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#else
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#define TRACE(...)
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#endif
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#ifndef MTD_SPI_NOR_WRITE_WAIT_US
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#define MTD_SPI_NOR_WRITE_WAIT_US (50 * US_PER_MS)
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#endif
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static int mtd_spi_nor_init(mtd_dev_t *mtd);
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static int mtd_spi_nor_read(mtd_dev_t *mtd, void *dest, uint32_t addr, uint32_t size);
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static int mtd_spi_nor_write(mtd_dev_t *mtd, const void *src, uint32_t addr, uint32_t size);
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static int mtd_spi_nor_erase(mtd_dev_t *mtd, uint32_t addr, uint32_t size);
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static int mtd_spi_nor_power(mtd_dev_t *mtd, enum mtd_power_state power);
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const mtd_desc_t mtd_spi_nor_driver = {
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.init = mtd_spi_nor_init,
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.read = mtd_spi_nor_read,
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.write = mtd_spi_nor_write,
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.erase = mtd_spi_nor_erase,
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.power = mtd_spi_nor_power,
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};
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/**
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* @internal
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* @brief Send command opcode followed by address, followed by a read to buffer
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*
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* @param[in] dev pointer to device descriptor
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* @param[in] opcode command opcode
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* @param[in] addr address (big endian)
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* @param[out] dest read buffer
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* @param[in] count number of bytes to read after the address has been sent
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*/
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static void mtd_spi_cmd_addr_read(mtd_spi_nor_t *dev, uint8_t opcode,
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be_uint32_t addr, void* dest, uint32_t count)
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{
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TRACE("mtd_spi_cmd_addr_read: %p, %02x, (%02x %02x %02x %02x), %p, %" PRIu32 "\n",
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(void *)dev, (unsigned int)opcode, addr.u8[0], addr.u8[1], addr.u8[2],
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addr.u8[3], dest, count);
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uint8_t *addr_buf = &addr.u8[4 - dev->addr_width];
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if (ENABLE_TRACE) {
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TRACE("mtd_spi_cmd_addr_read: addr:");
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for (unsigned int i = 0; i < dev->addr_width; ++i)
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{
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TRACE(" %02x", addr_buf[i]);
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}
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TRACE("\n");
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}
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/* Acquire exclusive access to the bus. */
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spi_acquire(dev->spi, dev->cs, dev->mode, dev->clk);
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do {
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/* Send opcode followed by address */
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spi_transfer_byte(dev->spi, dev->cs, true, opcode);
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spi_transfer_bytes(dev->spi, dev->cs, true, (char *)addr_buf, NULL, dev->addr_width);
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/* Read data */
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spi_transfer_bytes(dev->spi, dev->cs, false, NULL, dest, count);
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} while(0);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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}
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/**
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* @internal
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* @brief Send command opcode followed by address, followed by a write from buffer
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*
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* @param[in] dev pointer to device descriptor
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* @param[in] opcode command opcode
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* @param[in] addr address (big endian)
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* @param[out] src write buffer
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* @param[in] count number of bytes to write after the opcode has been sent
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*/
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static void mtd_spi_cmd_addr_write(mtd_spi_nor_t *dev, uint8_t opcode,
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be_uint32_t addr, const void* src, uint32_t count)
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{
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TRACE("mtd_spi_cmd_addr_write: %p, %02x, (%02x %02x %02x %02x), %p, %" PRIu32 "\n",
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(void *)dev, (unsigned int)opcode, addr.u8[0], addr.u8[1], addr.u8[2],
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addr.u8[3], src, count);
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uint8_t *addr_buf = &addr.u8[4 - dev->addr_width];
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if (ENABLE_TRACE) {
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TRACE("mtd_spi_cmd_addr_write: addr:");
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for (unsigned int i = 0; i < dev->addr_width; ++i)
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{
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TRACE(" %02x", addr_buf[i]);
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}
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TRACE("\n");
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}
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/* Acquire exclusive access to the bus. */
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spi_acquire(dev->spi, dev->cs, dev->mode, dev->clk);
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do {
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/* Send opcode followed by address */
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spi_transfer_byte(dev->spi, dev->cs, true, opcode);
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bool cont = (count > 0); /* only keep CS asserted when there is data that follows */
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spi_transfer_bytes(dev->spi, dev->cs, cont, (char *)addr_buf, NULL, dev->addr_width);
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/* Write data */
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if (cont) {
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spi_transfer_bytes(dev->spi, dev->cs, false, (void *)src, NULL, count);
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}
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} while(0);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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}
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/**
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* @internal
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* @brief Send command opcode followed by a read to buffer
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*
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* @param[in] dev pointer to device descriptor
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* @param[in] opcode command opcode
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* @param[out] dest read buffer
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* @param[in] count number of bytes to write after the opcode has been sent
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*/
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static void mtd_spi_cmd_read(mtd_spi_nor_t *dev, uint8_t opcode, void* dest, uint32_t count)
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{
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TRACE("mtd_spi_cmd_read: %p, %02x, %p, %" PRIu32 "\n",
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(void *)dev, (unsigned int)opcode, dest, count);
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/* Acquire exclusive access to the bus. */
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spi_acquire(dev->spi, dev->cs, dev->mode, dev->clk);
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spi_transfer_regs(dev->spi, dev->cs, opcode, NULL, dest, count);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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}
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/**
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* @internal
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* @brief Send command opcode followed by a write from buffer
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*
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* @param[in] dev pointer to device descriptor
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* @param[in] opcode command opcode
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* @param[out] src write buffer
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* @param[in] count number of bytes to write after the opcode has been sent
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*/
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static void __attribute__((unused)) mtd_spi_cmd_write(mtd_spi_nor_t *dev, uint8_t opcode, const void* src, uint32_t count)
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{
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TRACE("mtd_spi_cmd_write: %p, %02x, %p, %" PRIu32 "\n",
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(void *)dev, (unsigned int)opcode, src, count);
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/* Acquire exclusive access to the bus. */
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spi_acquire(dev->spi, dev->cs, dev->mode, dev->clk);
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spi_transfer_regs(dev->spi, dev->cs, opcode, (void *)src, NULL, count);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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}
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/**
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* @internal
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* @brief Send command opcode
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*
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* @param[in] dev pointer to device descriptor
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* @param[in] opcode command opcode
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*/
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static void mtd_spi_cmd(mtd_spi_nor_t *dev, uint8_t opcode)
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{
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TRACE("mtd_spi_cmd: %p, %02x\n",
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(void *)dev, (unsigned int)opcode);
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/* Acquire exclusive access to the bus. */
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spi_acquire(dev->spi, dev->cs, dev->mode, dev->clk);
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spi_transfer_byte(dev->spi, dev->cs, false, opcode);
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/* Release the bus for other threads. */
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spi_release(dev->spi);
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}
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/**
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* @internal
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* @brief Compute 8 bit parity
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*/
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static inline uint8_t parity8(uint8_t x)
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{
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/* Taken from http://stackoverflow.com/a/21618038/1805713 */
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x ^= x >> 4;
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x ^= x >> 2;
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x ^= x >> 1;
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return (x & 1);
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}
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/**
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* @internal
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* @brief Read JEDEC ID
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*/
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static int mtd_spi_read_jedec_id(mtd_spi_nor_t *dev, mtd_jedec_id_t *out)
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{
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/* not using above read functions because of variable length rdid response */
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int status = 0;
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mtd_jedec_id_t jedec;
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DEBUG("mtd_spi_read_jedec_id: rdid=0x%02x\n", (unsigned int)dev->opcode->rdid);
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/* Acquire exclusive access to the bus. */
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spi_acquire(dev->spi, dev->cs, dev->mode, dev->clk);
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/* Send opcode */
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spi_transfer_byte(dev->spi, dev->cs, true, dev->opcode->rdid);
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/* Read manufacturer ID */
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jedec.bank = 1;
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while (status == 0) {
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jedec.manuf = spi_transfer_byte(dev->spi, dev->cs, true, 0);
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if (jedec.manuf == JEDEC_NEXT_BANK) {
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/* next bank, see JEP106 */
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DEBUG("mtd_spi_read_jedec_id: manuf bank incr\n");
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++jedec.bank;
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continue;
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}
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if (parity8(jedec.manuf) == 0) {
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/* saw even parity, we expected odd parity => parity error */
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DEBUG("mtd_spi_read_jedec_id: Parity error (0x%02x)\n", (unsigned int)jedec.manuf);
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status = -2;
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break;
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}
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else {
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/* all OK! */
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break;
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}
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}
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DEBUG("mtd_spi_read_jedec_id: bank=%u manuf=0x%02x\n", (unsigned int)jedec.bank,
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(unsigned int)jedec.manuf);
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/* Read device ID */
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if (status == 0) {
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spi_transfer_bytes(dev->spi, dev->cs, false, NULL, (char *)&jedec.device[0], sizeof(jedec.device));
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}
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DEBUG("mtd_spi_read_jedec_id: device=0x%02x, 0x%02x\n",
|
||||
(unsigned int)jedec.device[0], (unsigned int)jedec.device[1]);
|
||||
|
||||
if (status == 0) {
|
||||
*out = jedec;
|
||||
}
|
||||
|
||||
/* Release the bus for other threads. */
|
||||
spi_release(dev->spi);
|
||||
return status;
|
||||
}
|
||||
|
||||
static inline void wait_for_write_complete(mtd_spi_nor_t *dev)
|
||||
{
|
||||
do {
|
||||
uint8_t status;
|
||||
mtd_spi_cmd_read(dev, dev->opcode->rdsr, &status, sizeof(status));
|
||||
|
||||
TRACE("mtd_spi_nor: wait device status = 0x%02x\n", (unsigned int)status);
|
||||
if ((status & 1) == 0) { /* TODO magic number */
|
||||
break;
|
||||
}
|
||||
#if MODULE_XTIMER
|
||||
xtimer_usleep(MTD_SPI_NOR_WRITE_WAIT_US);
|
||||
#else
|
||||
thread_yield();
|
||||
#endif
|
||||
} while (1);
|
||||
}
|
||||
|
||||
static int mtd_spi_nor_init(mtd_dev_t *mtd)
|
||||
{
|
||||
DEBUG("mtd_spi_nor_init: %p\n", (void *)mtd);
|
||||
mtd_spi_nor_t *dev = (mtd_spi_nor_t *)mtd;
|
||||
|
||||
DEBUG("mtd_spi_nor_init: -> spi: %lx, cs: %lx, opcodes: %p\n",
|
||||
(unsigned long)dev->spi, (unsigned long)dev->cs, (void *)dev->opcode);
|
||||
|
||||
DEBUG("mtd_spi_nor_init: %" PRIu32 " bytes "
|
||||
"(%" PRIu32 " sectors, %" PRIu32 " bytes/sector, "
|
||||
"%" PRIu32 " pages, "
|
||||
"%" PRIu32 " pages/sector, %" PRIu32 " bytes/page)\n",
|
||||
mtd->pages_per_sector * mtd->sector_count * mtd->page_size,
|
||||
mtd->sector_count, mtd->pages_per_sector * mtd->page_size,
|
||||
mtd->pages_per_sector * mtd->sector_count,
|
||||
mtd->pages_per_sector, mtd->page_size);
|
||||
DEBUG("mtd_spi_nor_init: Using %u byte addresses\n", dev->addr_width);
|
||||
|
||||
if (dev->addr_width == 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* CS */
|
||||
DEBUG("mtd_spi_nor_init: CS init\n");
|
||||
spi_init_cs(dev->spi, dev->cs);
|
||||
|
||||
int res = mtd_spi_read_jedec_id(dev, &dev->jedec_id);
|
||||
if (res < 0) {
|
||||
return -EIO;
|
||||
}
|
||||
DEBUG("mtd_spi_nor_init: Found chip with ID: (%d, 0x%02x, 0x%02x, 0x%02x)\n",
|
||||
dev->jedec_id.bank, dev->jedec_id.manuf, dev->jedec_id.device[0], dev->jedec_id.device[1]);
|
||||
|
||||
uint8_t status;
|
||||
mtd_spi_cmd_read(dev, dev->opcode->rdsr, &status, sizeof(status));
|
||||
DEBUG("mtd_spi_nor_init: device status = 0x%02x\n", (unsigned int)status);
|
||||
|
||||
/* check whether page size and sector size are powers of two (most chips' are)
|
||||
* and compute the number of shifts needed to get the page and sector addresses
|
||||
* from a byte address */
|
||||
uint8_t shift = 0;
|
||||
uint32_t page_size = mtd->page_size;
|
||||
uint32_t mask = 0;
|
||||
if ((page_size & (page_size - 1)) == 0) {
|
||||
while ((page_size >> shift) > 1) {
|
||||
++shift;
|
||||
}
|
||||
mask = (UINT32_MAX << shift);
|
||||
}
|
||||
dev->page_addr_mask = mask;
|
||||
dev->page_addr_shift = shift;
|
||||
DEBUG("mtd_spi_nor_init: page_addr_mask = 0x%08" PRIx32 ", page_addr_shift = %u\n",
|
||||
mask, (unsigned int)shift);
|
||||
|
||||
mask = 0;
|
||||
shift = 0;
|
||||
uint32_t sector_size = mtd->page_size * mtd->pages_per_sector;
|
||||
if ((sector_size & (sector_size - 1)) == 0) {
|
||||
while ((sector_size >> shift) > 1) {
|
||||
++shift;
|
||||
}
|
||||
mask = (UINT32_MAX << shift);
|
||||
}
|
||||
dev->sec_addr_mask = mask;
|
||||
dev->sec_addr_shift = shift;
|
||||
|
||||
DEBUG("mtd_spi_nor_init: sec_addr_mask = 0x%08" PRIx32 ", sec_addr_shift = %u\n",
|
||||
mask, (unsigned int)shift);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtd_spi_nor_read(mtd_dev_t *mtd, void *dest, uint32_t addr, uint32_t size)
|
||||
{
|
||||
DEBUG("mtd_spi_nor_read: %p, %p, 0x%" PRIx32 ", 0x%" PRIx32 "\n",
|
||||
(void *)mtd, dest, addr, size);
|
||||
mtd_spi_nor_t *dev = (mtd_spi_nor_t *)mtd;
|
||||
size_t chipsize = mtd->page_size * mtd->pages_per_sector * mtd->sector_count;
|
||||
if (addr > chipsize) {
|
||||
return -EOVERFLOW;
|
||||
}
|
||||
if (size > mtd->page_size) {
|
||||
size = mtd->page_size;
|
||||
}
|
||||
if ((addr + size) > chipsize) {
|
||||
size = chipsize - addr;
|
||||
}
|
||||
uint32_t page_addr_mask = dev->page_addr_mask;
|
||||
if ((addr & page_addr_mask) != ((addr + size - 1) & page_addr_mask)) {
|
||||
/* Reads across page boundaries must be split */
|
||||
size = mtd->page_size - (addr & ~(page_addr_mask));
|
||||
}
|
||||
if (size == 0) {
|
||||
return 0;
|
||||
}
|
||||
be_uint32_t addr_be = byteorder_htonl(addr);
|
||||
mtd_spi_cmd_addr_read(dev, dev->opcode->read, addr_be, dest, size);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int mtd_spi_nor_write(mtd_dev_t *mtd, const void *src, uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t total_size = mtd->page_size * mtd->pages_per_sector * mtd->sector_count;
|
||||
DEBUG("mtd_spi_nor_write: %p, %p, 0x%" PRIx32 ", 0x%" PRIx32 "\n",
|
||||
(void *)mtd, src, addr, size);
|
||||
if (size == 0) {
|
||||
return 0;
|
||||
}
|
||||
mtd_spi_nor_t *dev = (mtd_spi_nor_t *)mtd;
|
||||
if (size > mtd->page_size) {
|
||||
DEBUG("mtd_spi_nor_write: ERR: page program >1 page (%" PRIu32 ")!\n", mtd->page_size);
|
||||
return -EOVERFLOW;
|
||||
}
|
||||
if (dev->page_addr_mask &&
|
||||
((addr & dev->page_addr_mask) != ((addr + size - 1) & dev->page_addr_mask))) {
|
||||
DEBUG("mtd_spi_nor_write: ERR: page program spans page boundary!\n");
|
||||
return -EOVERFLOW;
|
||||
}
|
||||
if (addr + size > total_size) {
|
||||
return -EOVERFLOW;
|
||||
}
|
||||
be_uint32_t addr_be = byteorder_htonl(addr);
|
||||
|
||||
/* write enable */
|
||||
mtd_spi_cmd(dev, dev->opcode->wren);
|
||||
|
||||
/* Page program */
|
||||
mtd_spi_cmd_addr_write(dev, dev->opcode->page_program, addr_be, src, size);
|
||||
|
||||
/* waiting for the command to complete before returning */
|
||||
wait_for_write_complete(dev);
|
||||
return size;
|
||||
}
|
||||
|
||||
static int mtd_spi_nor_erase(mtd_dev_t *mtd, uint32_t addr, uint32_t size)
|
||||
{
|
||||
DEBUG("mtd_spi_nor_erase: %p, 0x%" PRIx32 ", 0x%" PRIx32 "\n",
|
||||
(void *)mtd, addr, size);
|
||||
mtd_spi_nor_t *dev = (mtd_spi_nor_t *)mtd;
|
||||
uint32_t sector_size = mtd->page_size * mtd->pages_per_sector;
|
||||
uint32_t total_size = sector_size * mtd->sector_count;
|
||||
|
||||
if (dev->sec_addr_mask &&
|
||||
((addr & ~dev->sec_addr_mask) != 0)) {
|
||||
/* This is not a requirement in hardware, but it helps in catching
|
||||
* software bugs (the erase-all-your-files kind) */
|
||||
DEBUG("addr = %" PRIx32 " ~dev->erase_addr_mask = %" PRIx32 "", addr, ~dev->sec_addr_mask);
|
||||
DEBUG("mtd_spi_nor_erase: ERR: erase addr not aligned on %" PRIu32 " byte boundary.\n",
|
||||
sector_size);
|
||||
return -EOVERFLOW;
|
||||
}
|
||||
if (addr + size > total_size) {
|
||||
return -EOVERFLOW;
|
||||
}
|
||||
be_uint32_t addr_be = byteorder_htonl(addr);
|
||||
|
||||
/* write enable */
|
||||
mtd_spi_cmd(dev, dev->opcode->wren);
|
||||
|
||||
if (size == total_size) {
|
||||
mtd_spi_cmd_addr_write(dev, dev->opcode->chip_erase, addr_be, NULL, 0);
|
||||
}
|
||||
else if ((dev->flag & SPI_NOR_F_SECT_4K) && size == 4096) {
|
||||
/* 4 KiO sectors can be erased with sector erase command */
|
||||
mtd_spi_cmd_addr_write(dev, dev->opcode->sector_erase, addr_be, NULL, 0);
|
||||
}
|
||||
else if ((dev->flag & SPI_NOR_F_SECT_32K) && size == 32768) {
|
||||
/* 32 KiO sectors can be erased with sector erase command */
|
||||
mtd_spi_cmd_addr_write(dev, dev->opcode->block_erase_32k, addr_be, NULL, 0);
|
||||
}
|
||||
else if (size % sector_size != 0) {
|
||||
return -EOVERFLOW;
|
||||
}
|
||||
else {
|
||||
for (size_t i = 0; i < size / sector_size; i++) {
|
||||
mtd_spi_cmd_addr_write(dev, dev->opcode->block_erase, addr_be, NULL, 0);
|
||||
addr += sector_size;
|
||||
addr_be = byteorder_htonl(addr);
|
||||
}
|
||||
}
|
||||
|
||||
/* waiting for the command to complete before returning */
|
||||
wait_for_write_complete(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtd_spi_nor_power(mtd_dev_t *mtd, enum mtd_power_state power)
|
||||
{
|
||||
mtd_spi_nor_t *dev = (mtd_spi_nor_t *)mtd;
|
||||
|
||||
switch (power) {
|
||||
case MTD_POWER_UP:
|
||||
mtd_spi_cmd(dev, dev->opcode->wake);
|
||||
break;
|
||||
case MTD_POWER_DOWN:
|
||||
mtd_spi_cmd(dev, dev->opcode->sleep);
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
45
drivers/mtd_spi_nor/mtd_spi_nor_configs.c
Normal file
45
drivers/mtd_spi_nor/mtd_spi_nor_configs.c
Normal file
@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Eistec AB
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup drivers_mtd_spi_nor
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Configurations for some known serial flash memory devices
|
||||
*
|
||||
* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "mtd_spi_nor.h"
|
||||
|
||||
/* Define opcode tables for SPI NOR flash memory devices here. */
|
||||
|
||||
/* Linker garbage collection (gcc -fdata-sections -Wl,--gc-sections) should ensure
|
||||
* that only the tables that are actually used by the application will take up
|
||||
* space in the .rodata section in program ROM. */
|
||||
|
||||
const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default = {
|
||||
.rdid = 0x9f,
|
||||
.wren = 0x06,
|
||||
.rdsr = 0x05,
|
||||
.wrsr = 0x01,
|
||||
.read = 0x03,
|
||||
.read_fast = 0x0b,
|
||||
.page_program = 0x02,
|
||||
.sector_erase = 0x20,
|
||||
.block_erase_32k = 0x52,
|
||||
.block_erase = 0xd8,
|
||||
.chip_erase = 0xc7,
|
||||
.sleep = 0xb9,
|
||||
.wake = 0xab,
|
||||
};
|
||||
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue
Block a user