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Merge pull request #6066 from neiljay/pr/add_mips-pic32_mz

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cpu: Add PIC32MZ support
This commit is contained in:
Hauke Petersen 2017-03-29 12:53:47 +02:00 committed by GitHub
commit 76bae4b111
30 changed files with 59703 additions and 51 deletions
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2
boards/pic32-wifire/Makefile Normal file
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MODULE = board
include $(RIOTBASE)/Makefile.base

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boards/pic32-wifire/Makefile.features Normal file
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# Various other features (if any)
FEATURES_PROVIDED += cpp
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = mips32r2

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boards/pic32-wifire/Makefile.include Normal file
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export CPU = mips_pic32mz
export CPU_MODEL=p32mz2048efg100
export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/
export APPDEPS += $(RIOTCPU)/$(CPU)/$(CPU_MODEL)/$(CPU_MODEL).S

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boards/pic32-wifire/include/board.h Normal file
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/*
* Copyright(C) 2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @defgroup boards_pic32-wifire Digilent PIC32 WiFire
* @ingroup boards
* @brief board configuration for the Digilent PIC32 WiFire
* @details
* See:
* http://store.digilentinc.com/chipkit-wi-fire-wifi-enabled-mz-microcontroller-board/
* for more information on the board.
*
* @{
*
* @file
* @brief board configuration for the Digilent PIC32 WiFire
*
* @author Neil Jones <Neil.Jones@imgtec.com>
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "vendor/p32mz2048efg100.h"
/**
* @brief Set how many increments of the count register per uS
* needed by the timer code.
*/
#define TICKS_PER_US (100)
/**
* @brief We are using an External Interrupt Controller (all pic32 devices use this mode)
*/
#define EIC_IRQ (1)
/**
* @brief Board level initialisation
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* _BOARD_H_ */
/** @} */

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boards/pic32-wifire/include/periph_conf.h Normal file
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/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @defgroup boards_pic32-wifire Digilent PIC32 WiFire
* @ingroup boards
* @brief peripheral configuration for the Digilent PIC32 WiFire
* @{
*
* @file
* @brief peripheral configuration for the Digilent PIC32 WiFire
*
* @author Neil Jones <Neil.Jones@imgtec.com>
*/
#ifndef _PERIPH_CONF_H_
#define _PERIPH_CONF_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief The peripheral clock is required for the UART Baud rate calculation
* It is configured by the 'config' registers (see pic32_config_settings.c)
*/
#define PERIPHERAL_CLOCK (100000000) /* Hz */
/**
* @brief Timer definitions
* @{
*/
#define TIMER_NUMOF (1)
#define TIMER_0_CHANNELS (3)
/** @} */
/**
* @brief UART Definitions
* There are 6 UARTS available on this CPU.
* We route debug via UART4 on this board,
* this is the UART connected to the FTDI USB <-> UART device.
*
* Note Microchip number the UARTS 1->4.
* @{
*/
#define UART_NUMOF (6)
#define DEBUG_VIA_UART (4)
#define DEBUG_UART_BAUD (9600)
/** @} */
#ifdef __cplusplus
}
#endif
#endif
/** @} */

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boards/pic32-wifire/pic32_config_settings.c Normal file
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/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <stdint.h>
#include "vendor/p32mz2048efg100.h"
/*
* Note banked access only applies to MZ part MX only has 1 set of registers
* similar to the MZ's lower alias.Thus when working with MX parts comment
* out the *_B* entries, note the address in the comments are different for MX
* too so a different linker script is required between MX and MZ to place
* these registers at the correct addresses. MM parts have completely different
* config registers, so this file is not applicable.
*
* Note when programming via Microchip IPE (tested using a Pickit-3) entries
* need to exist in the programming file for both the lower alias and the
* config1 configuration spaces (starting at 0x1FC0FFC0 and 0x1FC4FFC0)
* hence the duplicate entries in different sections allowing the linker to
* place them at different addresses.
*/
/*
* DEVCFG3_LA @ 0x1FC0FFC0 (lower alias)
* ADEVFGC3_LA @ 0x1FC0FF40 (alternate devcfg3 in lower alias)
* DEVCFG3_B1 @ 0x1FC4FFC0 (config space 1)
* ADEVCFG3_B1 @ 0x1FC4FF40 (alternate devcfg3 in config space 1)
* DEVCFG3_B2 @ 0x1FC6FFC0 (config space 1)
* ADEVCFG3_B2 @ 0x1FC6FF40 (alternate devcfg3 in config space 2)
*
*
* USERID
* FMIIEN OFF Ethernet RMII/MII Enable RMII Enabled
* FETHIO ON Ethernet I/O Pin Select Default Ethernet I/O
* PGL1WAY OFF Permission Group Lock One Way Configuration Allow multiple reconfigurations
* PMDL1WAY OFF Peripheral Module Disable Configuration Allow multiple reconfigurations
* IOL1WAY OFF Peripheral Pin Select Configuration Allow multiple reconfigurations
* FUSBIDIO OFF USB USBID Selection Controlled by Port Function
*/
volatile uint32_t DEVCFG3_LA __attribute__((used, section(".devcfg3_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION)
& (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION)
& (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION)
& (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION)
& (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION)
& (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION)
& (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION);
volatile uint32_t ADEVCFG3_LA __attribute__((used, section(".adevcfg3_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION)
& (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION)
& (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION)
& (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION)
& (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION)
& (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION)
& (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION);
volatile uint32_t DEVCFG3_B1 __attribute__((used, section(".devcfg3_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION)
& (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION)
& (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION)
& (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION)
& (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION)
& (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION)
& (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION);
volatile uint32_t ADEVCFG3_B1 __attribute__((used, section(".adevcfg3_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION)
& (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION)
& (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION)
& (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION)
& (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION)
& (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION)
& (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION);
/*
* Not needed by default:
* volatile uint32_t DEVCFG3_B2 __attribute__((used,section(".devcfg3_b2")))
* = DEVCFG3_LA;
* volatile uint32_t ADEVCFG3_B2 __attribute__((used,section(".adevcfg3_la")))
* = DEVCFG3_LA;
*
*/
/*
* DEVCFG2_LA @ 0x1FC0FFC4 (lower alias)
* ADEVFGC2_LA @ 0x1FC0FF44 (alternate devcfg2 in lower alias)
* DEVCFG2_B1 @ 0x1FC4FFC4 (config space 1)
* ADEVCFG2_B1 @ 0x1FC4FF44 (alternate devcfg2 in config space 1)
* DEVCFG2_B2 @ 0x1FC6FFC4 (config space 1)
* ADEVCFG2_B2 @ 0x1FC6FF44 (alternate devcfg2 in config space 2)
*
* 24MHz OSC / 3 * 50 / 2 = 200MHz
*
* FPLLIDIV DIV_3 System PLL Input Divider 3x Divider
* FPLLRNG RANGE_5_10_MHZ System PLL Input Range 5-10 MHz Input
* FPLLICLK PLL_POSC System PLL Input Clock Selection POSC is input to the System PLL
* FPLLMULT MUL_50 System PLL Multiplier PLL Multiply by 50
* FPLLODIV DIV_2 System PLL Output Clock Divider 2x Divider
* UPLLFSEL FREQ_24MHZ USB PLL Input Frequency Selection USB PLL input is 24 MHz
*/
volatile uint32_t DEVCFG2_LA __attribute__ ((used, section(".devcfg2_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION)
& (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION)
& (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION)
& (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION)
& (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION)
& (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION);
volatile uint32_t ADEVCFG2_LA __attribute__ ((used, section(".adevcfg2_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION)
& (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION)
& (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION)
& (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION)
& (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION)
& (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION);
volatile uint32_t DEVCFG2_B1 __attribute__ ((used, section(".devcfg2_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION)
& (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION)
& (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION)
& (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION)
& (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION)
& (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION);
volatile uint32_t ADEVCFG2_B1 __attribute__ ((used, section(".adevcfg2_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION)
& (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION)
& (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION)
& (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION)
& (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION)
& (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION);
/* Not needed by default: */
/* uint32_t DEVCFG2_B2 __attribute__ ((section(".devcfg2_b2"))) = DEVCFG2_LA; */
/* uint32_t ADEVCFG2_B2 __attribute__ ((section(".adevcfg2_b2"))) = DEVCFG2_LA; */
/*
* DEVCFG1_LA @ 0x1FC0FFC8 (lower alias)
* ADEVFGC1_LA @ 0x1FC0FF48 (alternate devcfg1 in lower alias)
* DEVCFG1_B1 @ 0x1FC4FFC8 (config space 1)
* ADEVCFG1_B1 @ 0x1FC4FF48 (alternate devcfg1 in config space 1)
* DEVCFG1_B2 @ 0x1FC6FFC8 (config space 1)
* ADEVCFG1_B2 @ 0x1FC6FF48 (alternate devcfg1 in config space 2)
*
* FNOSC SPLL Oscillator Selection Bits System PLL
* DMTINTV WIN_127_128 DMT Count Window Interval Window/Interval value is 127/128 counter value
* FSOSCEN OFF Secondary Oscillator Enable Disable SOSC
* IESO ON Internal/External Switch Over Enabled
* POSCMOD EC Primary Oscillator Configuration External clock mode
* OSCIOFNC OFF CLKO Output Signal Active on the OSCO Pin Disabled (1)
* FCKSM CSDCMD Clock Switching and Monitor Selection Clock Switch Disabled, FSCM Disabled
* WDTPS PS1048576 Watchdog Timer Postscaler 1:1048576
* WDTSPGM STOP Watchdog Timer Stop During Flash Programming WDT stops during Flash programming
* WINDIS NORMAL Watchdog Timer Window Mode Watchdog Timer is in non-Window mode
* FWDTEN OFF Watchdog Timer Enable WDT Disabled
* FWDTWINSZ WINSZ_25 Watchdog Timer Window Size Window size is 25%
* DMTCNT DMT8 Deadman Timer Count Selection 2^8 (256)
* FDMTEN OFF Deadman Timer Enable Deadman Timer is disabled
*/
volatile uint32_t DEVCFG1_LA __attribute__ ((used, section(".devcfg1_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION)
& (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION)
& (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION)
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION)
& (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION)
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION)
& (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION)
& (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION)
& (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION)
& (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION)
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION)
& (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION)
& (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION)
& (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION);
volatile uint32_t ADEVCFG1_LA __attribute__ ((used, section(".adevcfg1_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION)
& (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION)
& (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION)
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION)
& (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION)
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION)
& (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION)
& (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION)
& (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION)
& (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION)
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION)
& (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION)
& (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION)
& (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION);
volatile uint32_t DEVCFG1_B1 __attribute__ ((used, section(".devcfg1_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION)
& (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION)
& (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION)
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION)
& (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION)
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION)
& (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION)
& (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION)
& (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION)
& (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION)
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION)
& (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION)
& (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION)
& (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION);
volatile uint32_t ADEVCFG1_B1 __attribute__ ((used, section(".adevcfg1_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION)
& (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION)
& (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION)
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION)
& (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION)
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION)
& (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION)
& (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION)
& (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION)
& (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION)
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION)
& (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION)
& (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION)
& (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION);
/* Not needed by default: */
/* uint32_t DEVCFG1_B2 __attribute__ ((section(".devcfg1_b2"))) = DEVCFG1_LA; */
/* uint32_t ADEVCFG1_B2 __attribute__ ((section(".adevcfg1_b2"))) = DEVCFG1_LA */
/*
* DEVCFG0_LA @ 0x1FC0FFCC (lower alias)
* ADEVFGC0_LA @ 0x1FC0FF4C (alternate devcfg0 in lower alias)
* DEVCFG0_B1 @ 0x1FC4FFCC (config space 1)
* ADEVCFG0_B1 @ 0x1FC4FF4C (alternate devcfg0 in config space 1)
* DEVCFG0_B2 @ 0x1FC6FFCC (config space 1)
* ADEVCFG0_B2 @ 0x1FC6FF4C (alternate devcfg0 in config space 2)
*
* DEBUG OFF Background Debugger Enable Debugger is disabled
* JTAGEN ON JTAG Enable JTAG Port Enabled
* ICESEL ICS_PGx2 ICE/ICD Comm Channel Select Communicate on PGEC2/PGED2
* TRCEN ON Trace Enable Trace features in the CPU are disabled
* BOOTISA MIPS32 Boot ISA Selection Boot code and Exception code is MIPS32
* FECCCON OFF_UNLOCKED Dynamic Flash ECC Configuration ECC and Dynamic ECC are disabled (ECCCON bits are writable)
* FSLEEP OFF Flash Sleep Mode Flash is powered down when the device is in Sleep mode
* DBGPER PG_ALL Debug Mode CPU Access Permission Allow CPU access to all permission regions
* SMCLR MCLR_NORM Soft Master Clear Enable bit MCLR pin generates a normal system Reset
* SOSCGAIN GAIN_2X Secondary Oscillator Gain Control bits 2x gain setting
* SOSCBOOST ON Secondary Oscillator Boost Kick Start Enable bit Boost the kick start of the oscillator
* POSCGAIN GAIN_2X Primary Oscillator Gain Control bits 2x gain setting
* POSCBOOST ON Primary Oscillator Boost Kick Start Enable bit Boost the kick start of the oscillator
* EJTAGBEN NORMAL EJTAG Boot Normal EJTAG functionality
*/
volatile uint32_t DEVCFG0_LA __attribute__ ((used, section(".devcfg0_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION)
& (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION)
& (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION)
& (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION)
& (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION)
& (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION)
& (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION)
& (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION)
& (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION)
& (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION)
& (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION)
& (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION)
& (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION)
& (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION);
volatile uint32_t ADEVCFG0_LA __attribute__ ((used, section(".adevcfg0_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION)
& (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION)
& (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION)
& (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION)
& (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION)
& (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION)
& (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION)
& (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION)
& (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION)
& (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION)
& (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION)
& (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION)
& (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION)
& (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION);
volatile uint32_t DEVCFG0_B1 __attribute__ ((used, section(".devcfg0_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION)
& (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION)
& (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION)
& (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION)
& (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION)
& (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION)
& (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION)
& (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION)
& (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION)
& (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION)
& (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION)
& (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION)
& (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION)
& (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION);
volatile uint32_t ADEVCFG0_B1 __attribute__ ((used, section(".adevcfg0_b1")))=
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION)
& (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION)
& (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION)
& (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION)
& (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION)
& (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION)
& (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION)
& (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION)
& (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION)
& (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION)
& (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION)
& (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION)
& (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION)
& (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION);
/*
* uint32_t DEVCFG0_B2 __attribute__ ((section(".devcfg0_b2")))
* = 0xFFFFF7D7;
* uint32_t ADEVCFG0_B2 __attribute__ ((section(".adevcfg0_b2")))
* = 0xFFFFF7D7;
*
*/
/*
* DEVCP0_LA @ 0x1FC0FFDC (lower alias)
* ADEVCP0_LA @ 0x1FC0FF5C (alternate devcp0 in lower alias)
* DEVCP0_B1 @ 0x1FC4FFDC (config space 1)
* ADEVCP0_B1 @ 0x1FC4FF5C (alternate devcp0 in config space 1)
* DEVCP0_B2 @ 0x1FC6FFDC (config space 1)
* ADEVCP0_B2 @ 0x1FC6FF5C (alternate devcp0 in config space 2
*
* CP OFF Code Protect Protection Disabled, unused bits must be 1.
*/
volatile uint32_t DEVCP0_LA __attribute__ ((used, section(".devcp0_la"))) =
0xFFFFFFFF | _DEVCP0_CP_MASK;
volatile uint32_t ADEVCP0_LA __attribute__ ((used, section(".adevcp0_la"))) =
0xFFFFFFFF | _DEVCP0_CP_MASK;
volatile uint32_t DEVCP0_B1 __attribute__ ((used, section(".devcp0_b1"))) =
0xFFFFFFFF | _DEVCP0_CP_MASK;
volatile uint32_t ADEVCP0_B1 __attribute__ ((used, section(".adevcp0_b1"))) =
0xFFFFFFFF | _DEVCP0_CP_MASK;
/* not needed by default */
/* uint32_t DEVCP0_B2 __attribute__ ((section(".devcp0_b1"))) = 0xFFFFFFFF; */
/* uint32_t ADEVCP0_B2 __attribute__ ((section(".adevcp0_b1"))) = 0xFFFFFFFF; */
/*
* SEQ_B1[0..3] @ 1FC0FFF0
* SEQ_B1[0..3] @ 1FC4FFF0
*
* TSEQ Boot Flash True Sequence Number
* CSEQ Boot Flash Complement Sequence Number
*/
volatile uint32_t SEQ_LA[4] __attribute__ ((used, section(".seq_la"))) =
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
volatile uint32_t SEQ_B1[4] __attribute__ ((used, section(".seq_b1"))) =
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
/*
* Not needed by default:
* uint32_t SEQ_B2[4] __attribute__ ((section(".seq_b2"))) =
* {0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF};
*/
/*
* STUPIDLY Microchip has hard coded the MSB bit of devsign to 0, So even if
* you erase the whole device, everything returns 0xFFFFFFF except this 1
* register (and its alternate) which return 0x7FFFFFF!!
*
* We set it in the output image so verification doesn't fail
*
* DEVSIGN0 @ 0xBFC0FFEC
* ADEVSIGN0 @ 0xBFC0FF6C
*
*/
volatile uint32_t DEVSIGN_LA __attribute__ ((used, section(".devsign_la"))) = 0x7FFFFFFF;
volatile uint32_t ADEVSIGN_LA __attribute__ ((used, section(".adevsign_la"))) = 0x7FFFFFFF;
volatile uint32_t DEVSIGN_B1 __attribute__ ((used, section(".devsign_b1"))) = 0x7FFFFFFF;
volatile uint32_t ADEVSIGN_B1 __attribute__ ((used, section(".adevsign_b1"))) = 0x7FFFFFFF;
volatile uint32_t DEVSIGN_B2 __attribute__ ((used, section(".devsign_b2"))) = 0x7FFFFFFF;
volatile uint32_t ADEVSIGN_B2 __attribute__ ((used, section(".adevsign_b2"))) = 0x7FFFFFFF;
/*
* Without a reference to this function from elsewhere LD throws the whole
* compile unit away even though the data is 'volatile' and 'used' !!!
*/
void dummy(void)
{
(void)1;
}

45
boards/pic32-wifire/wifire.c Normal file
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@ -0,0 +1,45 @@
/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <stdio.h>
#include <stdint.h>
#include "periph/uart.h"
#include "bitarithm.h"
#include "board.h"
#include "periph_conf.h"
extern void dummy(void);
void board_init(void)
{
/*
* Setup pin mux for UART4 this is the one connected
* to the ftdi chip (usb<->uart)
*/
U4RXREG = 0xb; /* connect pin RPF2 to UART 4 RX */
RPF8R = 0x2; /* connect pin RPF8 to UART 4 TX */
PORTFCLR = BIT8 | BIT2; /* clear down port F pins 2 and 8 */
TRISFCLR = BIT2; /* set portf pin 2 as input */
TRISFSET = BIT8; /* set portf pin 8 as output */
ODCFCLR = BIT8 | BIT2; /* set portf pint 2 and 8 as not open-drain */
/* intialise UART used for debug (printf) */
#ifdef DEBUG_VIA_UART
uart_init(DEBUG_VIA_UART, DEBUG_UART_BAUD, NULL, 0);
#endif
/* Stop the linker from throwing away the PIC32 config register settings */
dummy();
}
void pm_reboot(void)
{
/* TODO, note this is needed to get 'default' example to build */
}

43
cpu/Makefile.include.mips_common Normal file
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@ -0,0 +1,43 @@
ifndef MIPS_ELF_ROOT
ifneq ($(BUILD_IN_DOCKER),1) #Don't error when BUILD_IN_DOCKER=1 as it _is_ set in DOCKER
$(error "Please set $$(MIPS_ELF_ROOT) and ensure $$(MIPS_ELF_ROOT)/bin is on your PATH")
endif
endif
# Target triple for the build.
export TARGET_ARCH ?= mips-mti-elf
export ABI=32
ifneq ($(BUILD_IN_DOCKER),1) #Don't error when BUILD_IN_DOCKER=1 as MIPS_ELF_ROOT _is_ set in DOCKER
include $(MIPS_ELF_ROOT)/share/mips/rules/mipshal.mk
endif
# define build specific options
export CFLAGS_CPU = -EL -std=gnu99
export CFLAGS_LINK = -ffunction-sections -fno-builtin -fshort-enums #-fdata-sections
export CFLAGS_DBG = -O0 -g2
export CFLAGS_OPT = -Os -g2
export CFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_OPT)
#$(CFLAGS_DBG)
ifeq ($(USE_HARD_FLOAT),1)
export CFLAGS += -mhard-float
else
export CFLAGS += -msoft-float #hard-float is the default so we must set soft-float
export LINKFLAGS += -msoft-float
endif
ifeq ($(USE_DSP),1)
export CFLAGS += -mdsp
endif
export ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_OPT) #$(CFLAGS_DBG)
export LINKFLAGS += $(MIPS_HAL_LDFLAGS) -mabi=$(ABI)
export LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT)
export LINKFLAGS += -Wl,--gc-sections
# This CPU implementation is using the new core/CPU interface:
export CFLAGS += -DCOREIF_NG=1

42
cpu/mips32r2_common/Makefile.include
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@ -1,48 +1,8 @@
ifndef MIPS_ELF_ROOT
$(error "Please set $$(MIPS_ELF_ROOT) and ensure $$(MIPS_ELF_ROOT)/bin is on your PATH")
endif
# Target triple for the build.
export TARGET_ARCH ?= mips-mti-elf
export ABI=32
export MEMORY_BASE=0x80000000
export MEMORY_SIZE=1M
export APP_START=0x80000000
include $(MIPS_ELF_ROOT)/share/mips/rules/mipshal.mk
include $(RIOTCPU)/Makefile.include.mips_common
# define build specific options
export CFLAGS_CPU = -EL -march=mips32r2 -std=gnu99
export CFLAGS_LINK = -ffunction-sections -fdata-sections -fno-builtin -fshort-enums
export CFLAGS_DBG = -O0 -g2
export CFLAGS_OPT = -Os -g2
export CFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_OPT)
#$(CFLAGS_DBG)
ifeq ($(USE_HARD_FLOAT),1)
export CFLAGS += -mhard-float
else
export CFLAGS += -msoft-float #hard-float is the default so we must set soft-float
export LINKFLAGS += -msoft-float
endif
ifeq ($(USE_DSP),1)
export CFLAGS += -mdsp
endif
export ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_OPT) #$(CFLAGS_DBG)
export LINKFLAGS += $(MIPS_HAL_LDFLAGS) -mabi=$(ABI)
export LINKFLAGS += -Tuhi32.ld
export LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT)
export LINKFLAGS += -Wl,--gc-sections
# This CPU implementation is using the new core/CPU interface:
export CFLAGS += -DCOREIF_NG=1
# use newlib as libc, Actually use toolchains newlib.
#export USEMODULE += newlib
export USEMODULE += periph

69
cpu/mips32r2_common/include/eic_irq.h Normal file
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@ -0,0 +1,69 @@
/*
* Copyright 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup cpu_mips32r2_commom MIPS32R2 Common
* @ingroup cpu
* @{
*
* @file
* @brief API for supporting External Interrupt Controllers (EIC mode)
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef EIC_IRQ_H_
#define EIC_IRQ_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ brief Internal Interrupt numbers
*
* MIPS cores have a few internally generated interrupts from the Timer,
* Performance Counters and Fast Debug Channel hardware, in EIC mode these
* become outputs from the core and are connected to the external controller,
* the external control then loops these back at whichever IPL it decides
*
* We use negative numbers to represent these, leaving positive numbers free for
* the SoC specific interrupts
* @{
*/
#define EIC_IRQ_TIMER (-1)
#define EIC_IRQ_FDC (-2)
#define EIC_IRQ_PC (-3)
/** @} */
/**
* @brief Configure and route the interrupt
*/
void eic_irq_configure(int irq_num);
/**
* @brief Enable an interrupt
*/
void eic_irq_enable(int irq_num);
/**
* @brief Disable an interrupt
*/
void eic_irq_disable(int irq_num);
/**
* @brief Acknowledge an interrupt
*/
void eic_irq_ack(int irq_num);
#ifdef __cplusplus
}
#endif
#endif
/** @} */

48
cpu/mips32r2_common/periph/timer.c
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@ -21,9 +21,12 @@
#include "irq.h"
#include "timex.h"
#include "div.h"
#include <sys/time.h>
#ifdef EIC_IRQ
#include "../include/eic_irq.h"
#endif
/*
* setting TIMER_ACCURACY_SHIFT lower will improve accuracy
* at the cost of more regular interrupts (hence less power efficient).
@ -40,7 +43,8 @@
/*
* The base MIPS count / compare timer is fixed frequency at core clock / 2
* and is pretty basic This timer is currently only supported in Vectored
* Interrupt Mode (VI), EIC mode is not supported yet.
* Interrupt Mode (VI), EIC mode is partially supported in non-vectored mode
* only.
*
* RIOT's xtimer expects the timer to operate at 1MHZ or any 2^n multiple or
* factor of this, thus we maintain a software timer which counts at 1MHz.
@ -76,7 +80,7 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
{
assert(dev == 0);
(void)freq; /*Cannot adjust Frequency */
(void)freq; /* Cannot adjust Frequency */
timer_isr_ctx.cb = cb;
timer_isr_ctx.arg = arg;
@ -93,7 +97,11 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
mips32_bc_c0(C0_CAUSE, CR_DC);
/* Enable Timer Interrupts */
#ifdef EIC_IRQ
eic_irq_configure(EIC_IRQ_TIMER);
#else
mips32_bs_c0(C0_STATUS, SR_HINT5);
#endif
return 0;
@ -160,20 +168,52 @@ void timer_stop(tim_t dev)
void timer_irq_enable(tim_t dev)
{
#ifdef EIC_IRQ
eic_irq_enable(EIC_IRQ_TIMER);
#else
mips32_bs_c0(C0_STATUS, SR_HINT5);
#endif
}
void timer_irq_disable(tim_t dev)
{
#ifdef EIC_IRQ
eic_irq_disable(EIC_IRQ_TIMER);
#else
mips32_bc_c0(C0_STATUS, SR_HINT5);
#endif
}
/* note Compiler inserts GP context save + restore code (to current stack). */
#ifdef EIC_IRQ
/*
* This is a hack - currently the toolchain does not support correct placement
* of EIC mode vectors (it is coming though) But we can support non-vectored EIC
* mode and note the default PIC32 interrupt controller (which uses EIC +
* MCU-ASE) defaults to non vectored mode anyway with all interrupts coming via
* vector 0 which is equivalent to 'sw0' in 'VI' mode.
*
* Thus all EIC interrupts should be decoded here (currently only Timer is
* used)
*
* When toolchain support is available we could move to full vector mode but
* this does take up significant space (MCU-ASE provides 256 vectors at 32B
* spacing (the default) thats 8KB of vector space!), So a single entry point
* may be better anyway.
*
*/
void __attribute__ ((interrupt("vector=sw0"), keep_interrupts_masked)) _mips_isr_sw0(void)
#else
void __attribute__ ((interrupt("vector=hw5"))) _mips_isr_hw5(void)
#endif
{
register int cr = mips_getcr();
if (cr & CR_TI) {
#ifdef EIC_IRQ
eic_irq_ack(EIC_IRQ_TIMER);
#endif
uint32_t status = irq_arch_disable();
counter += TIMER_ACCURACY;
irq_arch_restore(status);

2
cpu/mips_pic32_common/Makefile Normal file
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@ -0,0 +1,2 @@
DIRS += periph
include $(RIOTBASE)/Makefile.base

7
cpu/mips_pic32_common/Makefile.include Normal file
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@ -0,0 +1,7 @@
# depends on mips32r2_common
USEMODULE += mips32r2_common
export MIPS32R2_COMMON = $(RIOTCPU)/mips32r2_common/
export INCLUDES = $(MIPS32R2_COMMON)include
include $(MIPS32R2_COMMON)Makefile.include

3
cpu/mips_pic32_common/periph/Makefile Normal file
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@ -0,0 +1,3 @@
MODULE = periph
include $(RIOTBASE)/Makefile.base

77
cpu/mips_pic32_common/periph/uart.c Normal file
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@ -0,0 +1,77 @@
/*
* Copyright(C) 2016,2017 Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <assert.h>
#include "periph/uart.h"
#include "board.h"
#define UxMODE(U) (U.regs[0x00/4])
#define UxMODECLR(U) (U.regs[0x04/4])
#define UxMODESET(U) (U.regs[0x08/4])
#define UxSTA(U) (U.regs[0x10/4])
#define UxSTACLR(U) (U.regs[0x14/4])
#define UxSTASET(U) (U.regs[0x18/4])
#define UxTXREG(U) (U.regs[0x20/4])
#define UxRXREG(U) (U.regs[0x30/4])
#define UxBRG(U) (U.regs[0x40/4])
#define REGS_SPACING (_UART2_BASE_ADDRESS - _UART1_BASE_ADDRESS)
/* PERIPHERAL_CLOCK must be defined in board file */
typedef struct PIC32_UART_tag {
volatile uint32_t *regs;
uint32_t clock;
} PIC32_UART_T;
/* pic uarts are numbered 1 to 6 */
static PIC32_UART_T pic_uart[UART_NUMOF + 1];
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
assert(uart <= UART_NUMOF && uart != 0); /*No uart 0 on pic32*/
/* Pin Mux should be setup in board file */
pic_uart[uart].regs =
(volatile uint32_t *)(_UART1_BASE_ADDRESS + (uart - 1) * REGS_SPACING);
pic_uart[uart].clock = PERIPHERAL_CLOCK;
UxBRG(pic_uart[uart])= (pic_uart[uart].clock / (16 * baudrate)) - 1;
UxSTA(pic_uart[uart])= 0;
UxMODE(pic_uart[uart])= _U1MODE_ON_MASK;
UxSTASET(pic_uart[uart])= _U1STA_URXEN_MASK;
UxSTASET(pic_uart[uart])= _U1STA_UTXEN_MASK;
return 0;
}
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
assert(uart <= UART_NUMOF && uart != 0);
while(len--) {
while(UxSTA(pic_uart[uart])& _U1STA_UTXBF_MASK) {}
UxTXREG(pic_uart[uart]) = *data++;
}
}
void uart_poweron(uart_t uart)
{
assert(uart <= UART_NUMOF && uart != 0);
UxMODESET(pic_uart[uart])= _U1MODE_ON_MASK;
}
void uart_poweroff(uart_t uart)
{
assert(uart <= UART_NUMOF && uart != 0);
UxMODECLR(pic_uart[uart])= _U1MODE_ON_MASK;
}

244
cpu/mips_pic32_common/reset_mod.S Normal file
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@ -0,0 +1,244 @@
/*
* Copyright 2014-2015, Imagination Technologies Limited and/or its
* affiliated group companies.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* ************ PLEASE READ ME !!!! ****************
This file is a copy of the reset_mod.S from $MIPS_ELF_ROOT/share/mips/boot
(from the 2016.05-03 version) with a couple of modifications:
#define SKIP_COPY_TO_RAM - prevents the bootloader copying the whole contents
of flash to ram (as we want to XIP from flash), we copy initialised data from
flash to ram in 'software_init_hook'.
move .org's to before the labels to make the vector labels appear at the vector
addresses.
In boot_debug_exception vector drop out of debug mode before spining, this allows
attachment of an external debug program to investigate a hung system.
Future toolchain versions will have these changes included and this file will
be no longer needed.
Note the above copyright/license is 3 Clause BSD and as such is compatible with LGPLv2.1
as such we grant licensing this file under LGPLv2.1 (See the file LICENSE in the top level
directory for more details) as well.
Thanks for reading.
*/
#define _RESETCODE
.set nomips16
#include <mips/regdef.h>
#include <mips/cpu.h>
#include <mips/asm.h>
.set push
.set nomicromips
LEAF(__reset_vector)
lui a2, %hi(__cpu_init)
addiu a2, %lo(__cpu_init)
mtc0 $0, C0_COUNT # Clear cp0 Count (Used to measure boot time.)
jr a2
.space 32 # Just to cope with a quirk of MIPS malta boards
# this can be deleted for anything else.
END(__reset_vector)
.set pop
LEAF(__cpu_init)
# Verify the code is here due to a reset and not NMI. If this is an NMI then trigger
# a debugger breakpoint using a sdbp instruction.
mfc0 s1, C0_STATUS # Read CP0 Status
ext s1, s1, SR_NMI_SHIFT, 1 # extract NMI
beqz s1, init_resources # /* Branch if this is NOT an NMI exception. */
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
init_resources:
# Init CP0 Status, Count, Compare, Watch*, and Cause.
jal __init_cp0
# Initialise L2/L3 cache
# This could be done from cached code if there is a cca override or similar
# Determine L2/L3 cache config.
lui a2, %hi(__init_l23cache)
addiu a2, a2, %lo(__init_l23cache)
jal a2
init_ic:
# Initialize the L1 instruction cache.
jal __init_icache
# The changing of Kernel mode cacheability must be done from KSEG1
# Since the code is executing from KSEG0 It needs to do a jump to KSEG1 change K0
# and jump back to KSEG0
lui a2, %hi(__change_k0_cca)
addiu a2, a2, %lo(__change_k0_cca)
li a1, 0xf
ins a2, a1, 29, 1 # changed to KSEG1 address by setting bit 29
jalr a2
.weak __init_l23cache_cached
lui a2, %hi(__init_l23cache_cached)
addiu a2, a2, %lo(__init_l23cache_cached)
beqz a2, init_dc
jal a2
init_dc:
# Initialize the L1 data cache
jal __init_dcache
# Initialize the TLB.
jal __init_tlb
# Allow everything else to be initialized via a hook.
.weak __boot_init_hook
lui a2, %hi(__boot_init_hook)
addiu a2, a2, %lo(__boot_init_hook)
beqz a2, 1f
jalr a2
1:
#ifndef SKIP_COPY_TO_RAM
# Copy code and data to RAM
li s1, 0xffffffff
# Copy code and read-only/initialized data from FLASH to (uncached) RAM.
lui a1, %hi(__flash_app_start)
addiu a1, a1, %lo(__flash_app_start)
ins a1, s1, 29, 1 # Make it uncached (kseg1)
lui a2, %hi(__app_start)
addiu a2, a2, %lo(__app_start)
ins a2, s1, 29, 1 # Make it uncached (kseg1)
lui a3, %hi(_edata)
addiu a3, a3, %lo(_edata)
ins a3, s1, 29, 1 # Make it uncached (kseg1)
beq a2, a3, $Lcopy_to_ram_done
$Lnext_ram_word:
lw a0, 0(a1)
sw a0, 0(a2)
addiu a2, a2, 4
addiu a1, a1, 4
bne a3, a2, $Lnext_ram_word
$Lcopy_to_ram_done:
#endif
# Prepare for eret to _start
lui ra, %hi($Lall_done) # If main returns then go to all_done.
addiu ra, ra, %lo($Lall_done)
lui v0, %hi(_start) # Load the address of _start
addiu v0, v0, %lo(_start)
mtc0 v0, C0_ERRPC # Set ErrorEPC to _start
ehb # Clear hazards (makes sure write to ErrorPC has completed)
li a0, 0 # UHI compliant null argument setup
# Return from exception will now execute the application startup code
eret
$Lall_done:
# If _start returns it will return to this point.
# Just spin here reporting the exit.
li $25, 1 # UHI exit operation
move $4, v0 # /* Collect exit code for UHI exit */
sdbbp 1 # Invoke UHI operation
b $Lall_done
END(__cpu_init)
/**************************************************************************************
B O O T E X C E P T I O N H A N D L E R S (CP0 Status[BEV] = 1)
**************************************************************************************/
/* NOTE: the linker script must insure that this code starts at start + 0x200 so the exception */
/* vectors will be addressed properly. All .org assume this! */
/* TLB refill, 32 bit task. */
.org 0x200 # TLB refill, 32 bit task.
LEAF(__boot_tlb_refill)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_tlb_refill)
.org 0x280 # XTLB refill, 64 bit task. BEV + 0x280
LEAF(__boot_xtlb_refill)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_xtlb_refill)
.org 0x300 # Cache error exception. BEV + 0x300
LEAF(__boot_cache_error)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_cache_error)
.org 0x380 # General exception. BEV + 0x380
LEAF(__boot_general_exception)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_general_exception)
# If you want the above code to fit into 1k flash you will need to leave
# out the code below. This is the code that covers the debug exception
# which you normally will not get.
.org 0x480
LEAF(__boot_debug_exception)
# EJTAG Debug (with ProbEn = 0 in the EJTAG Control Register)
mfc0 k1, C0_DEPC # Save Debug exception point in DESAVE
mtc0 k1, C0_DESAVE
LA k1, 1f
# Drop out of debug mode before spinning (To allow a JTAG probe in).
mtc0 k1, C0_DEPC
ehb
deret
1:
b 1b #Spin indefinately
END(__boot_debug_exception)

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MODULE = cpu
USEMODULE += mips_pic32_common
USEMODULE += mips32r2_common
DIRS += $(RIOTCPU)/mips_pic32_common $(RIOTCPU)/mips32r2_common
include $(RIOTBASE)/Makefile.base

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export MEMORY_BASE=0x80000000
export MEMORY_SIZE=512K
export APP_START=0x80000000
export ROMABLE = 1
include $(RIOTCPU)/Makefile.include.mips_common
# define build specific options
export CFLAGS += -march=m5101 -mmicromips -DSKIP_COPY_TO_RAM
export CFLAGS += -DMIPS_MICROMIPS
export USEMODULE += periph
export LINKFLAGS += -Wl,--defsym,__use_excpt_boot=0 $(CFLAGS)
export LINKFLAGS += -T$(RIOTCPU)/$(CPU)/ldscripts/pic32mz2048_uhi.ld
# the pickit programmer (MPLAB-IPE) wants physical addresses in the hex file!!
export OBJCOPY = objcopy #use system objcopy as toolchain one is broken.
export OFLAGS += -O ihex \
--change-section-lma .lowerbootflashalias-0xA0000000 \
--change-section-lma .bootflash1-0xA0000000 \
--change-section-lma .bootflash2-0xA0000000 \
--change-section-lma .exception_vector-0x80000000 \
--change-section-lma .text-0x80000000 \
--change-section-lma .init-0x80000000 \
--change-section-lma .fini-0x80000000 \
--change-section-lma .eh_frame-0x80000000 \
--change-section-lma .gcc_except_table-0x80000000 \
--change-section-lma .jcr-0x80000000 \
--change-section-lma .ctors-0x80000000 \
--change-section-lma .dtors-0x80000000 \
--change-section-lma .rodata-0x80000000 \
--change-section-lma .data-0x80000000 \
--change-section-lma .bss-0x80000000 \
--change-section-lma .startdata-0x80000000

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/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <assert.h>
#include "board.h"
#include "../mips32r2_common/include/eic_irq.h"
void eic_irq_configure(int irq_num)
{
/* Only timer interrupt supported currently */
assert(irq_num == EIC_IRQ_TIMER);
/* Enable IRQ0 CPU Timer Interrupt */
IEC0SET = _IEC0_CTIE_MASK;
/* Set IRQ 0 to priority 1.0 */
IPC0SET = 1 << _IPC0_CTIP_POSITION | 0 << _IPC0_CTIS_POSITION;
}
void eic_irq_enable(int irq_num)
{
/* Only timer interrupt supported currently */
assert(irq_num == EIC_IRQ_TIMER);
/* Enable IRQ0 CPU Timer Interrupt */
IEC0SET = _IEC0_CTIE_MASK;
}
void eic_irq_disable(int irq_num)
{
/* Only timer interrupt supported currently */
assert(irq_num == EIC_IRQ_TIMER);
/* Disable IRQ0 CPU Timer Interrupt */
IEC0CLR = _IEC0_CTIE_MASK;
}
void eic_irq_ack(int irq_num)
{
/* Only timer interrupt supported currently */
assert(irq_num == EIC_IRQ_TIMER);
/* Ack the timer interrupt */
IFS0CLR =_IFS0_CTIF_MASK;
}

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/*
* Copyright(C) 2017, 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @defgroup cpu_mips_pic32mz MIPS PIC32MZ
* @ingroup cpu
* @{
*
* @file
* @brief main CPU definitions for pic32mz devices.
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef CPU_H_
#define CPU_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdio.h>
#include <inttypes.h>
#include <assert.h>
#include "irq.h"
/**
* @brief We run from flash on PIC32
*/
#define FLASH_XIP (1)
/**
* @brief Print the last instruction's address
*
* @todo: Not supported
*/
static inline void cpu_print_last_instruction(void)
{
/* This function must exist else RIOT won't compile */
}
#ifdef __cplusplus
}
#endif
#endif
/** @} */

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/*
* Copyright(C) 2017, 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @defgroup cpu_mips_pic32mz MIPS PIC32MZ
* @ingroup cpu
* @{
*
* @file
* @brief CPU definitions for pic32mz devices.
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef _CPU_CONF_H_
#define _CPU_CONF_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configuration of default stack sizes
*
* printf takes a pretty tortured route through the C lib
* then via UHI syscall exception to end up at the UART
* driver.
*
* When debugging timer code we get printfs on the idle threads
* stack which can easily blow its limits.
*
* Note code must be compiled at -Os with these values, using -O0
* you'll overflow these stacks.
*
* NO ISR stack is in use yet, interrupt use the current running stack
* hence the big-ish default stack size.
* @{
*/
#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
#define THREAD_EXTRA_STACKSIZE_PRINTF (1024)
#endif
#ifndef THREAD_STACKSIZE_DEFAULT
#define THREAD_STACKSIZE_DEFAULT (2048)
#endif
#ifndef THREAD_STACKSIZE_IDLE
#ifdef NDEBUG
#define THREAD_STACKSIZE_IDLE (512)
#else
#define THREAD_STACKSIZE_IDLE (512 + THREAD_EXTRA_STACKSIZE_PRINTF)
#endif
#endif
#define ISR_STACKSIZE (0)
/** @} */
#ifdef __cplusplus
}
#endif
#endif
/** @} */

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/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/* This file must exist to get timer code to build */
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif

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/*
* A platform and target independent link script to produce UHI
* compliant binaries with varying levels of system initialization
* support.
*/
__entry = DEFINED(__reset_vector) ? 0xbfc00000 : _start;
ENTRY(__entry)
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips")
GROUP(-lc -luhi -lgcc -lhal)
SEARCH_DIR(.)
__DYNAMIC = 0;
STARTUP(crt0.o)
/* Force the exception handler to be registered */
EXTERN(__register_excpt_handler)
/* Force the exception handler to be included in the link */
EXTERN(__exception_entry)
/*
* Require verbose exceptions. This can be changed to pull in
* __exception_handle_quiet to reduce code size but be less
* informative
*/
EXTERN(__exception_handle_verbose)
/* Force the interrupt handlers to tbe included in the link */
EXTERN(__isr_vec)
/* Require the UHI getargs support */
EXTERN(__getargs)
/*
* Set the location of the top of the stack. A value of 0 means
* that it will be automatically placed at the highest address
* available as described by the __memory_* setttings
*/
PROVIDE (__stack = 0);
/* Size of the memory returned by _get_ram_range */
PROVIDE (__memory_size = 512K);
/* Base of the memory returned by _get_ram_range */
PROVIDE (__memory_base = 0x80000000);
/* Stride length for tlb software invalidate for tlbinvf
* (mipsXXr3+). Some MIPS implementations may layout the sets/ways
* differently in the index register. Either sets LSB or ways LSB.
*
* By setting this to 1 we presume that sets come first. The default boot
* code will decrement this value from the Number of TLB entries.
*/
PROVIDE (__tlb_stride_length = 1);
/* By default, XPA is not used even if available. To enable XPA,
* __enable_xpa should be 1.
*/
PROVIDE (__enable_xpa = 0);
/*
* 0 = Do not use exception handler present in boot for UHI
* 1 = Use exception handler present in boot for UHI if BEV is 0 at
* startup
* 2 = Always use exception handler present in boot for UHI
*/
PROVIDE (__use_excpt_boot = 0);
/*
* Include the code to be able to return to boot context. This is
* necessary if __use_excpt_boot != 0.
*/
EXTERN (__register_excpt_boot);
ASSERT (DEFINED(__register_excpt_boot) || __use_excpt_boot == 0,
"Registration for boot context is required for UHI chaining")
/* Control if subnormal floating-point values are flushed to zero in
hardware. This applies to both FPU and MSA operations. */
PROVIDE (__flush_to_zero = 1);
/* Set up the public symbols depending on whether the user has chosen
quiet or verbose exception handling above */
EXTERN (__exception_handle);
PROVIDE(__exception_handle = (DEFINED(__exception_handle_quiet)
? __exception_handle_quiet
: __exception_handle_verbose));
PROVIDE(_mips_handle_exception = __exception_handle);
/*
* Initalize some symbols to be zero so we can reference them in the
* crt0 without core dumping. These functions are all optional, but
* we do this so we can have our crt0 always use them if they exist.
* This is so BSPs work better when using the crt0 installed with gcc.
* We have to initalize them twice, so we multiple object file
* formats, as some prepend an underscore.
*/
PROVIDE (hardware_exit_hook = 0);
PROVIDE (hardware_hazard_hook = 0);
PROVIDE (hardware_init_hook = 0);
PROVIDE (software_init_hook = 0);
/* The default base address for application flash code is 0x9D001000 */
PROVIDE (__app_start = 0x9D001000) ;
/* Set default vector spacing to 32 bytes. */
PROVIDE (__isr_vec_space = 32);
/* Leave space for 9 vector entries by default. 8 entry points and one
fallback handler. */
PROVIDE (__isr_vec_count = 9);
/*
* The start of boot flash must be set if including boot code. By default
* the use of boot code will mean that application code is copied
* from flash to RAM at runtime before being executed.
*/
PROVIDE (__lower_boot_flash_start = DEFINED(__reset_vector) ? 0xbfc00000 : __app_start);
PROVIDE (__boot_flash1_start = 0xbfc40000);
PROVIDE (__boot_flash2_start = 0xbfc60000);
PROVIDE (__bev_override = 0x9fc00000);
PROVIDE (__flash_vector_start = 0x9D000000);
PROVIDE (__flash_app_start = 0x9D001000);
SECTIONS
{
/* Start of bootrom */
.lowerbootflashalias __bev_override : /* Runs uncached (from 0xBfc00000) until I$ is
initialized. */
AT (__lower_boot_flash_start)
{
__base = .;
*(.reset) /* Reset entry point. */
*(.boot) /* Boot code. */
. = ALIGN(8);
. = __base + 0xff40; /*Alternate Config bits (lower Alias)*/
KEEP(*(.adevcfg3_la))
KEEP(*(.adevcfg2_la))
KEEP(*(.adevcfg1_la))
KEEP(*(.adevcfg0_la))
. = __base + 0xff5c;
KEEP(*(.adevcp0_la))
. = __base + 0xff6c;
KEEP(*(.adevsign_la))
. = __base + 0xffc0; /*Config bits (lower Alias)*/
KEEP(*(.devcfg3_la))
KEEP(*(.devcfg2_la))
KEEP(*(.devcfg1_la))
KEEP(*(.devcfg0_la))
. = __base + 0xffdc;
KEEP(*(.devcp0_la))
. = __base + 0xffec;
KEEP(*(.devsign_la))
. = __base + 0xfff0;
KEEP(*(.seq_la))
} = 0xFFFFFFFF
/*
* We only add this block to keep the MPLAB programmer happy
* It seems to want the config regs values in the non aliased locations
*/
. = __base + 0x40000 + 0xff40;
.bootflash1 :
AT(__boot_flash1_start + 0xff40)
{
__altbase = .;
. = __altbase; /* Alternate Config Bits (boot flash 1) */
KEEP(*(.adevcfg3_b1))
KEEP(*(.adevcfg2_b1))
KEEP(*(.adevcfg1_b1))
KEEP(*(.adevcfg0_b1))
. = __altbase + 0x1c;
KEEP(*(.adevcp0_b1))
. = __altbase + 0x2c;
KEEP(*(.adevsign_b1))
. = __altbase + 0x80;
KEEP(*(.devcfg3_b1))
KEEP(*(.devcfg2_b1))
KEEP(*(.devcfg1_b1))
KEEP(*(.devcfg0_b1))
. = __altbase + 0x9c;
KEEP(*(.devcp0_b1))
. = __altbase + 0xAc;
KEEP(*(.devsign_b1))
. = __altbase + 0xB0;
KEEP(*(.seq_b1))
} = 0xFFFFFFFF
/*
* We only add this block to keep the MPLAB programmer happy
* It seems to want the config regs values in the non aliased locations
*/
. = __base + 0x60000 + 0xff40;
.bootflash2 :
AT(__boot_flash2_start + 0xff40)
{
__altbase = .;
. = __altbase; /* Alternate Config Bits (boot flash 1) */
KEEP(*(.adevcfg3_b2))
KEEP(*(.adevcfg2_b2))
KEEP(*(.adevcfg1_b2))
KEEP(*(.adevcfg0_b2))
. = __altbase + 0x1c;
KEEP(*(.adevcp0_b2))
. = __altbase + 0x2c;
KEEP(*(.adevsign_b2))
. = __altbase + 0x80;
KEEP(*(.devcfg3_b2))
KEEP(*(.devcfg2_b2))
KEEP(*(.devcfg1_b2))
KEEP(*(.devcfg0_b2))
. = __altbase + 0x9c;
KEEP(*(.devcp0_b2))
. = __altbase + 0xAc;
KEEP(*(.devsign_b2))
. = __altbase + 0xB0;
KEEP(*(.seq_b2))
} = 0xFFFFFFFF
/* Start of the application */
.exception_vector ALIGN(__flash_vector_start, 0x1000) :
AT (__flash_vector_start)
{
PROVIDE (__excpt_ebase = ABSOLUTE(.));
__base = .;
KEEP(* (.text.__exception_entry))
. = __base + 0x200;
KEEP(* (SORT(.text.__isr_vec*)))
/* Leave space for all the vector entries */
. = __base + 0x200 + (__isr_vec_space * __isr_vec_count);
ASSERT(__isr_vec_space == (DEFINED(__isr_vec_sw0)
? __isr_vec_sw1 - __isr_vec_sw0
: __isr_vec_space),
"Actual ISR vector spacing does not match __isr_vec_space");
ASSERT(__base + 0x200 == (DEFINED(__isr_vec_sw0)
? __isr_vec_sw0 & 0xfffffffe : __base + 0x200),
"__isr_vec_sw0 is not placed at EBASE + 0x200");
. = ALIGN(8);
} = 0
. = __flash_app_start;
.text : {
_ftext = . ;
PROVIDE (eprol = .);
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.mips16.fn.*)
*(.mips16.call.*)
}
.init : {
KEEP (*(.init))
}
.fini : {
KEEP (*(.fini))
}
.rel.sdata : {
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
}
PROVIDE (etext = .);
_etext = .;
.eh_frame_hdr : { *(.eh_frame_hdr) }
.eh_frame : { KEEP (*(.eh_frame)) }
.gcc_except_table : { *(.gcc_except_table*) }
.jcr : { KEEP (*(.jcr)) }
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
}
. = .;
.MIPS.abiflags : {
__MIPS_abiflags_start = .;
*(.MIPS.abiflags)
__MIPS_abiflags_end = .;
}
.rodata : {
*(.rdata)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
}
_rom_data_copy = .;
.data ALIGN(__memory_base + 0x1000, 16) :
AT (_rom_data_copy)
{
_fdata = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
_gp = . + 0x8000;
__global = _gp;
*(.lit8)
*(.lit4)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
}
. = ALIGN(4);
PROVIDE (edata = .);
_edata = .;
_fbss = .;
.sbss : {
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
}
.bss : {
_bss_start = . ;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
}
. = ALIGN(4);
PROVIDE (end = .);
_end = .;
/* Now place the data that is only needed within start.S and can be
overwritten by the heap. */
.startdata : {
*(.startdata)
}
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to
the beginning of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* Special sections generated by gcc */
/* Newer GNU linkers strip by default */
.mdebug.abi32 0 : { KEEP(*(.mdebug.abi32)) }
.mdebug.abiN32 0 : { KEEP(*(.mdebug.abiN32)) }
.mdebug.abi64 0 : { KEEP(*(.mdebug.abi64)) }
.mdebug.abiO64 0 : { KEEP(*(.mdebug.abiO64)) }
.mdebug.eabi32 0 : { KEEP(*(.mdebug.eabi32)) }
.mdebug.eabi64 0 : { KEEP(*(.mdebug.eabi64)) }
.gcc_compiled_long32 0 : { KEEP(*(.gcc_compiled_long32)) }
.gcc_compiled_long64 0 : { KEEP(*(.gcc_compiled_long64)) }
}

1
cpu/mips_pic32mz/p32mz2048efg100/Makefile Normal file
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@ -0,0 +1 @@
include $(RIOTBASE)/Makefile.base

6288
cpu/mips_pic32mz/p32mz2048efg100/p32mz2048efg100.S Normal file
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File diff suppressed because it is too large Load Diff

2
examples/gnrc_border_router/Makefile
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@ -15,7 +15,7 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk maple-mini \
pca10005 spark-core stm32f0discovery telosb weio wsn430-v1_3b \
wsn430-v1_4 yunjia-nrf51822 z1
BOARD_BLACKLIST += mips-malta # No UART available.
BOARD_BLACKLIST += mips-malta pic32-wifire pic32-clicker# No full UART available.
# use ethos (ethernet over serial) for network communication and stdio over
# UART, but not on native, as native has a tap interface towards the host.

2
examples/javascript/Makefile
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@ -13,7 +13,7 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk maple-mini \
BOARD_BLACKLIST := arduino-duemilanove arduino-mega2560 arduino-uno chronos \
msb-430 msb-430h qemu-i386 telosb waspmote-pro wsn430-v1_3b \
wsn430-v1_4 z1
wsn430-v1_4 z1 pic32-wifire
# Comment this out to disable code in RIOT that does safety checking
# which is not needed in a production environment but helps in the

4
sys/posix/include/fcntl.h
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@ -15,10 +15,10 @@
* @see http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/fcntl.h.html
*/
/** @todo Remove ifdef BOARD_MIPS_MALTA special case after
/** @todo Remove ifdef __mips__ special case after
* [#6639](https://github.com/RIOT-OS/RIOT/pull/6639) is merged */
#ifndef DOXYGEN
#if defined(CPU_NATIVE) || MODULE_NEWLIB || defined(BOARD_MIPS_MALTA)
#if defined(CPU_NATIVE) || MODULE_NEWLIB || defined(__mips__)
/* If building on native or newlib we need to use the system header instead */
#pragma GCC system_header
/* without the GCC pragma above #include_next will trigger a pedantic error */

4
sys/posix/include/sys/statvfs.h
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@ -22,9 +22,9 @@
#define SYS_STATVFS_H_
#include <sys/types.h> /* for fsblkcnt_t, fsfilcnt_t */
/** @todo Remove ifdef BOARD_MIPS_MALTA special case after
/** @todo Remove ifdef __mips__ special case after
* [#6639](https://github.com/RIOT-OS/RIOT/pull/6639) is merged */
#if MODULE_NEWLIB || defined(BOARD_MIPS_MALTA)
#if MODULE_NEWLIB || defined(__mips__)
/* newlib support for fsblkcnt_t was only recently added to the newlib git
* repository, commit f3e587d30a9f65d0c6551ad14095300f6e81672e, 15 apr 2016.
* Will be included in release 2.5.0, around new year 2016/2017.