mirror of
https://github.com/RIOT-OS/RIOT.git
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boards/frdm-k22f: Add NXP FRDM-K22F development board
This commit is contained in:
Joakim Nohlgård
parent
57b32f5c66
commit
912e497423
@ -1,5 +1,6 @@
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# set default port depending on operating system
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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export FFLAGS = flash-elf
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3
boards/frdm-k22f/Makefile
Normal file
3
boards/frdm-k22f/Makefile
Normal file
@ -0,0 +1,3 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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4
boards/frdm-k22f/Makefile.dep
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4
boards/frdm-k22f/Makefile.dep
Normal file
@ -0,0 +1,4 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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USEMODULE += saul_adc
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endif
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18
boards/frdm-k22f/Makefile.features
Normal file
18
boards/frdm-k22f/Makefile.features
Normal file
@ -0,0 +1,18 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Various other features (if any)
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FEATURES_PROVIDED += cpp
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m4_1
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6
boards/frdm-k22f/Makefile.include
Normal file
6
boards/frdm-k22f/Makefile.include
Normal file
@ -0,0 +1,6 @@
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# define the cpu used by the board
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export CPU = k22f
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export CPU_MODEL = mk22fn512vlh12
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# Include default FRDM board config
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include $(RIOTBOARD)/frdm-common/Makefile.include
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68
boards/frdm-k22f/board.c
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68
boards/frdm-k22f/board.c
Normal file
@ -0,0 +1,68 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2014 PHYTEC Messtechnik GmbH
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_frdm-k64f
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* @{
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*
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* @file
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* @brief Board specific implementations for the FRDM-K22F
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*
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* @}
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*/
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#include <stdint.h>
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#include "board.h"
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#include "mcg.h"
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#include "periph/gpio.h"
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#define SIM_CLKDIV1_48MHZ (SIM_CLKDIV1_OUTDIV1(0) | \
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SIM_CLKDIV1_OUTDIV2(1) | \
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SIM_CLKDIV1_OUTDIV3(1) | \
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SIM_CLKDIV1_OUTDIV4(1))
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static void cpu_clock_init(void);
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void board_init(void)
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{
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/* initialize the clock system */
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cpu_clock_init();
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/* initialize the CPU core */
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cpu_init();
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/* initialize and turn off the on-board RGB-LED */
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gpio_init(LED0_PIN, GPIO_OUT);
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gpio_init(LED1_PIN, GPIO_OUT);
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gpio_init(LED2_PIN, GPIO_OUT);
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gpio_set(LED0_PIN);
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gpio_set(LED1_PIN);
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gpio_set(LED2_PIN);
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}
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/**
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* @brief Configure the controllers clock system
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*
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* | Clock name | Run mode frequency (max) | VLPR mode frequency (max) |
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*
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* | Core | 120 MHz | 4 MHz |
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* | System | 120 MHz | 4 MHz |
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* | Bus | 60 MHz | 4 MHz |
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* | FlexBus | 30 MHz | 800 kHz |
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* | Flash | 26.67 MHz | 4 MHz |
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*/
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static void cpu_clock_init(void)
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{
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/* setup system prescalers */
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SIM->CLKDIV1 = (uint32_t)SIM_CLKDIV1_48MHZ;
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kinetis_mcg_set_mode(KINETIS_MCG_PEE);
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}
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81
boards/frdm-k22f/include/adc_params.h
Normal file
81
boards/frdm-k22f/include/adc_params.h
Normal file
@ -0,0 +1,81 @@
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/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_frdm-k22f
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped ADC
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef ADC_PARAMS_H
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#define ADC_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief ADC configuration
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*/
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static const saul_adc_params_t saul_adc_params[] =
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{
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{
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.name = "ADC0_DP",
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.line = ADC_LINE(0),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "ADC0_DM",
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.line = ADC_LINE(1),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "ADC1_DP",
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.line = ADC_LINE(2),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "ADC1_DM",
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.line = ADC_LINE(3),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "A0",
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.line = ADC_LINE(4),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "A1",
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.line = ADC_LINE(5),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "A2",
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.line = ADC_LINE(6),
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.res = ADC_RES_16BIT,
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},
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{
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.name = "A3",
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.line = ADC_LINE(7),
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.res = ADC_RES_16BIT,
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ADC_PARAMS_H */
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/** @} */
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67
boards/frdm-k22f/include/board.h
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67
boards/frdm-k22f/include/board.h
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@ -0,0 +1,67 @@
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/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup boards_frdm-k22f NXP FRDM-K22F Board
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* @ingroup boards
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* @brief Board specific implementations for the FRDM-K22F
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* @{
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*
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* @file
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* @brief Board specific definitions for the FRDM-K22F
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "cpu.h"
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#include "periph_conf.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name LED pin definitions and handlers
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* @{
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*/
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#define LED0_PIN GPIO_PIN(PORT_A, 1)
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#define LED1_PIN GPIO_PIN(PORT_A, 2)
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#define LED2_PIN GPIO_PIN(PORT_D, 5)
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#define LED0_MASK (1 << 1)
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#define LED1_MASK (1 << 2)
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#define LED2_MASK (1 << 5)
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#define LED0_ON (GPIOB->PCOR = LED0_MASK)
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#define LED0_OFF (GPIOB->PSOR = LED0_MASK)
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#define LED0_TOGGLE (GPIOB->PTOR = LED0_MASK)
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#define LED1_ON (GPIOE->PCOR = LED1_MASK)
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#define LED1_OFF (GPIOE->PSOR = LED1_MASK)
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#define LED1_TOGGLE (GPIOE->PTOR = LED1_MASK)
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#define LED2_ON (GPIOB->PCOR = LED2_MASK)
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#define LED2_OFF (GPIOB->PSOR = LED2_MASK)
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#define LED2_TOGGLE (GPIOB->PTOR = LED2_MASK)
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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56
boards/frdm-k22f/include/gpio_params.h
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56
boards/frdm-k22f/include/gpio_params.h
Normal file
@ -0,0 +1,56 @@
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/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_frdm_k22f
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped GPIOs
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief LED configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "LED(red)",
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.pin = LED0_PIN,
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.mode = GPIO_OUT
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},
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{
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.name = "LED(green)",
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.pin = LED1_PIN,
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.mode = GPIO_OUT
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},
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{
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.name = "LED(blue)",
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.pin = LED2_PIN,
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.mode = GPIO_OUT
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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289
boards/frdm-k22f/include/periph_conf.h
Normal file
289
boards/frdm-k22f/include/periph_conf.h
Normal file
@ -0,0 +1,289 @@
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/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_frdm-k22f
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the FRDM-K22F
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define KINETIS_CPU_USE_MCG 1
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#define KINETIS_MCG_USE_ERC 1
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#define KINETIS_MCG_USE_PLL 1
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/* The crystal connected to OSC0 is 8 MHz */
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#define KINETIS_MCG_DCO_RANGE (48000000u)
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#define KINETIS_MCG_ERC_OSCILLATOR 1
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#define KINETIS_MCG_ERC_FRDIV 3 /* ERC divider = 256 */
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#define KINETIS_MCG_ERC_RANGE 1
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#define KINETIS_MCG_ERC_FREQ (40000000u)
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#define KINETIS_MCG_PLL_PRDIV 3 /* divide factor = 4 */
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#define KINETIS_MCG_PLL_VDIV0 0 /* multiply factor = 24 */
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#define KINETIS_MCG_PLL_FREQ (48000000u)
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#define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ
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#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define PIT_NUMOF (2U)
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#define PIT_CONFIG { \
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{ \
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.prescaler_ch = 0, \
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.count_ch = 1, \
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}, \
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{ \
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.prescaler_ch = 2, \
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.count_ch = 3, \
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}, \
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}
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#define LPTMR_NUMOF (1U)
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#define LPTMR_CONFIG { \
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{ \
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.dev = LPTMR0, \
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.irqn = LPTMR0_IRQn, \
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} \
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}
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#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
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#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
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#define PIT_ISR_0 isr_pit1
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#define PIT_ISR_1 isr_pit3
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#define LPTMR_ISR_0 isr_lptmr0
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = UART1,
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.freq = CLOCK_CORECLOCK,
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.pin_rx = GPIO_PIN(PORT_E, 1),
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.pin_tx = GPIO_PIN(PORT_E, 0),
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.pcr_rx = PORT_PCR_MUX(3),
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.pcr_tx = PORT_PCR_MUX(3),
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.irqn = UART1_RX_TX_IRQn,
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.scgc_addr = &SIM_SCGC4,
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.scgc_bit = SIM_SCGC4_UART1_SHIFT,
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.mode = UART_MODE_8N1,
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},
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};
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#define UART_0_ISR (isr_uart1_rx_tx)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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static const adc_conf_t adc_config[] = {
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/* dev, pin, channel */
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{ .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC0_DP0 */
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{ .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC0_DM0 */
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{ .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC1_DP0 */
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{ .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC1_DM0 */
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{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, /* PTB0 (Arduino A0) */
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{ .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, /* PTB1 (Arduino A1) */
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{ .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15 }, /* PTC1 (Arduino A2) */
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{ .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 4 }, /* PTC2 (Arduino A3) */
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};
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#define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
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/** @} */
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/**
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* @name DAC configuration
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* @{
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*/
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#define DAC_CONFIG {}
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#define DAC_NUMOF 0
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/** @} */
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/**
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* @name PWM configuration
|
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* @{
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*/
|
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static const pwm_conf_t pwm_config[] = {
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{
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.ftm = FTM0,
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.chan = {
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{ .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 6 },
|
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{ .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
|
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{ .pin = GPIO_PIN(PORT_D, 5), .af = 4, .ftm_chan = 5 },
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},
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.chan_numof = 3,
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.ftm_num = 0
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
|
||||
* Clock configuration values based on the configured 48Mhz module clock.
|
||||
*
|
||||
* Auto-generated by:
|
||||
* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
static const uint32_t spi_clk_config[] = {
|
||||
(
|
||||
SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */
|
||||
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) |
|
||||
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) |
|
||||
SPI_CTAR_PDT(0) | SPI_CTAR_DT(8)
|
||||
),
|
||||
(
|
||||
SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */
|
||||
SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) |
|
||||
SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) |
|
||||
SPI_CTAR_PDT(0) | SPI_CTAR_DT(6)
|
||||
),
|
||||
(
|
||||
SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */
|
||||
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) |
|
||||
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) |
|
||||
SPI_CTAR_PDT(1) | SPI_CTAR_DT(3)
|
||||
),
|
||||
(
|
||||
SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */
|
||||
SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) |
|
||||
SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) |
|
||||
SPI_CTAR_PDT(2) | SPI_CTAR_DT(0)
|
||||
),
|
||||
(
|
||||
SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */
|
||||
SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
|
||||
SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
|
||||
SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
|
||||
)
|
||||
};
|
||||
|
||||
static const spi_conf_t spi_config[] = {
|
||||
{
|
||||
.dev = SPI0,
|
||||
.pin_miso = GPIO_PIN(PORT_D, 3),
|
||||
.pin_mosi = GPIO_PIN(PORT_D, 2),
|
||||
.pin_clk = GPIO_PIN(PORT_D, 1),
|
||||
.pin_cs = {
|
||||
GPIO_PIN(PORT_C, 4),
|
||||
GPIO_PIN(PORT_D, 4),
|
||||
GPIO_UNDEF,
|
||||
GPIO_UNDEF,
|
||||
GPIO_UNDEF
|
||||
},
|
||||
.pcr = GPIO_AF_2,
|
||||
.simmask = SIM_SCGC6_SPI0_MASK
|
||||
}
|
||||
};
|
||||
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NUMOF (1U)
|
||||
#define I2C_CLK CLOCK_CORECLOCK
|
||||
#define I2C_0_EN 1
|
||||
#define I2C_IRQ_PRIO 1
|
||||
/* Low (10 kHz): MUL = 4, SCL divider = 1280, total: 5120 */
|
||||
#define KINETIS_I2C_F_ICR_LOW (0x35)
|
||||
#define KINETIS_I2C_F_MULT_LOW (2)
|
||||
/* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
|
||||
#define KINETIS_I2C_F_ICR_NORMAL (0x1F)
|
||||
#define KINETIS_I2C_F_MULT_NORMAL (1)
|
||||
/* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
|
||||
#define KINETIS_I2C_F_ICR_FAST (0x17)
|
||||
#define KINETIS_I2C_F_MULT_FAST (0)
|
||||
/* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
|
||||
#define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
|
||||
#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
|
||||
|
||||
/* I2C 0 device configuration */
|
||||
#define I2C_0_DEV I2C0
|
||||
#define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK))
|
||||
#define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK))
|
||||
#define I2C_0_IRQ I2C0_IRQn
|
||||
#define I2C_0_IRQ_HANDLER isr_i2c0
|
||||
/* I2C 0 pin configuration */
|
||||
#define I2C_0_PORT PORTB
|
||||
#define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
|
||||
#define I2C_0_PIN_AF 2
|
||||
#define I2C_0_SDA_PIN 3
|
||||
#define I2C_0_SCL_PIN 2
|
||||
#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name GPIO configuration
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RTT and RTC configuration
|
||||
* @{
|
||||
*/
|
||||
#define RTT_NUMOF (1U)
|
||||
#define RTC_NUMOF (1U)
|
||||
#define RTT_DEV RTC
|
||||
#define RTT_IRQ RTC_IRQn
|
||||
#define RTT_IRQ_PRIO 10
|
||||
#define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
|
||||
#define RTT_ISR isr_rtc
|
||||
#define RTT_FREQUENCY (1)
|
||||
#define RTT_MAX_VALUE (0xffffffff)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Random Number Generator configuration
|
||||
* @{
|
||||
*/
|
||||
#define KINETIS_RNGA RNG
|
||||
#define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
|
||||
#define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CONF_H */
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue
Block a user