From 912e4974239cf9314e33af4a932d00d687e2bccd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Mon, 1 May 2017 11:47:06 +0200 Subject: [PATCH] boards/frdm-k22f: Add NXP FRDM-K22F development board --- boards/frdm-common/Makefile.include | 1 + boards/frdm-k22f/Makefile | 3 + boards/frdm-k22f/Makefile.dep | 4 + boards/frdm-k22f/Makefile.features | 18 ++ boards/frdm-k22f/Makefile.include | 6 + boards/frdm-k22f/board.c | 68 ++++++ boards/frdm-k22f/include/adc_params.h | 81 +++++++ boards/frdm-k22f/include/board.h | 67 ++++++ boards/frdm-k22f/include/gpio_params.h | 56 +++++ boards/frdm-k22f/include/periph_conf.h | 289 +++++++++++++++++++++++++ 10 files changed, 593 insertions(+) create mode 100644 boards/frdm-k22f/Makefile create mode 100644 boards/frdm-k22f/Makefile.dep create mode 100644 boards/frdm-k22f/Makefile.features create mode 100644 boards/frdm-k22f/Makefile.include create mode 100644 boards/frdm-k22f/board.c create mode 100644 boards/frdm-k22f/include/adc_params.h create mode 100644 boards/frdm-k22f/include/board.h create mode 100644 boards/frdm-k22f/include/gpio_params.h create mode 100644 boards/frdm-k22f/include/periph_conf.h diff --git a/boards/frdm-common/Makefile.include b/boards/frdm-common/Makefile.include index 1b48574458..09674de75b 100644 --- a/boards/frdm-common/Makefile.include +++ b/boards/frdm-common/Makefile.include @@ -1,5 +1,6 @@ # set default port depending on operating system PORT_LINUX ?= /dev/ttyACM0 +PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*))) export FFLAGS = flash-elf diff --git a/boards/frdm-k22f/Makefile b/boards/frdm-k22f/Makefile new file mode 100644 index 0000000000..f8fcbb53a0 --- /dev/null +++ b/boards/frdm-k22f/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/frdm-k22f/Makefile.dep b/boards/frdm-k22f/Makefile.dep new file mode 100644 index 0000000000..2abcbc1548 --- /dev/null +++ b/boards/frdm-k22f/Makefile.dep @@ -0,0 +1,4 @@ +ifneq (,$(filter saul_default,$(USEMODULE))) + USEMODULE += saul_gpio + USEMODULE += saul_adc +endif diff --git a/boards/frdm-k22f/Makefile.features b/boards/frdm-k22f/Makefile.features new file mode 100644 index 0000000000..5cf7e4f9a1 --- /dev/null +++ b/boards/frdm-k22f/Makefile.features @@ -0,0 +1,18 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_cpuid +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_hwrng +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_pwm +FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_rtt +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# Various other features (if any) +FEATURES_PROVIDED += cpp + +# The board MPU family (used for grouping by the CI system) +FEATURES_MCU_GROUP = cortex_m4_1 diff --git a/boards/frdm-k22f/Makefile.include b/boards/frdm-k22f/Makefile.include new file mode 100644 index 0000000000..5251374c92 --- /dev/null +++ b/boards/frdm-k22f/Makefile.include @@ -0,0 +1,6 @@ +# define the cpu used by the board +export CPU = k22f +export CPU_MODEL = mk22fn512vlh12 + +# Include default FRDM board config +include $(RIOTBOARD)/frdm-common/Makefile.include diff --git a/boards/frdm-k22f/board.c b/boards/frdm-k22f/board.c new file mode 100644 index 0000000000..9d19449812 --- /dev/null +++ b/boards/frdm-k22f/board.c @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * Copyright (C) 2014 PHYTEC Messtechnik GmbH + * Copyright (C) 2017 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_frdm-k64f + * @{ + * + * @file + * @brief Board specific implementations for the FRDM-K22F + * + * @author Joakim Nohlgård + * + * @} + */ + +#include +#include "board.h" +#include "mcg.h" +#include "periph/gpio.h" + +#define SIM_CLKDIV1_48MHZ (SIM_CLKDIV1_OUTDIV1(0) | \ + SIM_CLKDIV1_OUTDIV2(1) | \ + SIM_CLKDIV1_OUTDIV3(1) | \ + SIM_CLKDIV1_OUTDIV4(1)) + +static void cpu_clock_init(void); + +void board_init(void) +{ + /* initialize the clock system */ + cpu_clock_init(); + /* initialize the CPU core */ + cpu_init(); + + /* initialize and turn off the on-board RGB-LED */ + gpio_init(LED0_PIN, GPIO_OUT); + gpio_init(LED1_PIN, GPIO_OUT); + gpio_init(LED2_PIN, GPIO_OUT); + gpio_set(LED0_PIN); + gpio_set(LED1_PIN); + gpio_set(LED2_PIN); +} + +/** + * @brief Configure the controllers clock system + * + * | Clock name | Run mode frequency (max) | VLPR mode frequency (max) | + * + * | Core | 120 MHz | 4 MHz | + * | System | 120 MHz | 4 MHz | + * | Bus | 60 MHz | 4 MHz | + * | FlexBus | 30 MHz | 800 kHz | + * | Flash | 26.67 MHz | 4 MHz | + */ +static void cpu_clock_init(void) +{ + /* setup system prescalers */ + SIM->CLKDIV1 = (uint32_t)SIM_CLKDIV1_48MHZ; + + kinetis_mcg_set_mode(KINETIS_MCG_PEE); +} diff --git a/boards/frdm-k22f/include/adc_params.h b/boards/frdm-k22f/include/adc_params.h new file mode 100644 index 0000000000..3a6157a1d7 --- /dev/null +++ b/boards/frdm-k22f/include/adc_params.h @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2017 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_frdm-k22f + * @{ + * + * @file + * @brief Board specific configuration of direct mapped ADC + * + * @author Joakim Nohlgård + */ + +#ifndef ADC_PARAMS_H +#define ADC_PARAMS_H + +#include "board.h" +#include "saul/periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief ADC configuration + */ +static const saul_adc_params_t saul_adc_params[] = +{ + { + .name = "ADC0_DP", + .line = ADC_LINE(0), + .res = ADC_RES_16BIT, + }, + { + .name = "ADC0_DM", + .line = ADC_LINE(1), + .res = ADC_RES_16BIT, + }, + { + .name = "ADC1_DP", + .line = ADC_LINE(2), + .res = ADC_RES_16BIT, + }, + { + .name = "ADC1_DM", + .line = ADC_LINE(3), + .res = ADC_RES_16BIT, + }, + { + .name = "A0", + .line = ADC_LINE(4), + .res = ADC_RES_16BIT, + }, + { + .name = "A1", + .line = ADC_LINE(5), + .res = ADC_RES_16BIT, + }, + { + .name = "A2", + .line = ADC_LINE(6), + .res = ADC_RES_16BIT, + }, + { + .name = "A3", + .line = ADC_LINE(7), + .res = ADC_RES_16BIT, + }, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ADC_PARAMS_H */ +/** @} */ diff --git a/boards/frdm-k22f/include/board.h b/boards/frdm-k22f/include/board.h new file mode 100644 index 0000000000..ed7949e939 --- /dev/null +++ b/boards/frdm-k22f/include/board.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2017 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup boards_frdm-k22f NXP FRDM-K22F Board + * @ingroup boards + * @brief Board specific implementations for the FRDM-K22F + * @{ + * + * @file + * @brief Board specific definitions for the FRDM-K22F + * + * @author Joakim Nohlgård + */ + +#ifndef BOARD_H +#define BOARD_H + +#include "cpu.h" +#include "periph_conf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @name LED pin definitions and handlers + * @{ + */ +#define LED0_PIN GPIO_PIN(PORT_A, 1) +#define LED1_PIN GPIO_PIN(PORT_A, 2) +#define LED2_PIN GPIO_PIN(PORT_D, 5) + +#define LED0_MASK (1 << 1) +#define LED1_MASK (1 << 2) +#define LED2_MASK (1 << 5) + +#define LED0_ON (GPIOB->PCOR = LED0_MASK) +#define LED0_OFF (GPIOB->PSOR = LED0_MASK) +#define LED0_TOGGLE (GPIOB->PTOR = LED0_MASK) + +#define LED1_ON (GPIOE->PCOR = LED1_MASK) +#define LED1_OFF (GPIOE->PSOR = LED1_MASK) +#define LED1_TOGGLE (GPIOE->PTOR = LED1_MASK) + +#define LED2_ON (GPIOB->PCOR = LED2_MASK) +#define LED2_OFF (GPIOB->PSOR = LED2_MASK) +#define LED2_TOGGLE (GPIOB->PTOR = LED2_MASK) +/** @} */ + +/** + * @brief Initialize board specific hardware, including clock, LEDs and std-IO + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/frdm-k22f/include/gpio_params.h b/boards/frdm-k22f/include/gpio_params.h new file mode 100644 index 0000000000..65481c1f47 --- /dev/null +++ b/boards/frdm-k22f/include/gpio_params.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2017 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_frdm_k22f + * @{ + * + * @file + * @brief Board specific configuration of direct mapped GPIOs + * + * @author Joakim Nohlgård + */ + +#ifndef GPIO_PARAMS_H +#define GPIO_PARAMS_H + +#include "board.h" +#include "saul/periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief LED configuration + */ +static const saul_gpio_params_t saul_gpio_params[] = +{ + { + .name = "LED(red)", + .pin = LED0_PIN, + .mode = GPIO_OUT + }, + { + .name = "LED(green)", + .pin = LED1_PIN, + .mode = GPIO_OUT + }, + { + .name = "LED(blue)", + .pin = LED2_PIN, + .mode = GPIO_OUT + }, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_PARAMS_H */ +/** @} */ diff --git a/boards/frdm-k22f/include/periph_conf.h b/boards/frdm-k22f/include/periph_conf.h new file mode 100644 index 0000000000..ad2640456e --- /dev/null +++ b/boards/frdm-k22f/include/periph_conf.h @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2017 Eistec AB + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_frdm-k22f + * @{ + * + * @file + * @name Peripheral MCU configuration for the FRDM-K22F + * + * @author Joakim Nohlgård + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @name Clock system configuration + * @{ + */ +#define KINETIS_CPU_USE_MCG 1 +#define KINETIS_MCG_USE_ERC 1 +#define KINETIS_MCG_USE_PLL 1 +/* The crystal connected to OSC0 is 8 MHz */ +#define KINETIS_MCG_DCO_RANGE (48000000u) +#define KINETIS_MCG_ERC_OSCILLATOR 1 +#define KINETIS_MCG_ERC_FRDIV 3 /* ERC divider = 256 */ +#define KINETIS_MCG_ERC_RANGE 1 +#define KINETIS_MCG_ERC_FREQ (40000000u) +#define KINETIS_MCG_PLL_PRDIV 3 /* divide factor = 4 */ +#define KINETIS_MCG_PLL_VDIV0 0 /* multiply factor = 24 */ +#define KINETIS_MCG_PLL_FREQ (48000000u) + +#define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ +#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2) +/** @} */ + +/** + * @name Timer configuration + * @{ + */ +#define PIT_NUMOF (2U) +#define PIT_CONFIG { \ + { \ + .prescaler_ch = 0, \ + .count_ch = 1, \ + }, \ + { \ + .prescaler_ch = 2, \ + .count_ch = 3, \ + }, \ +} +#define LPTMR_NUMOF (1U) +#define LPTMR_CONFIG { \ + { \ + .dev = LPTMR0, \ + .irqn = LPTMR0_IRQn, \ + } \ +} +#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF)) + +#define PIT_BASECLOCK (CLOCK_BUSCLOCK) +#define PIT_ISR_0 isr_pit1 +#define PIT_ISR_1 isr_pit3 +#define LPTMR_ISR_0 isr_lptmr0 +/** @} */ + +/** +* @name UART configuration +* @{ +*/ +static const uart_conf_t uart_config[] = { + { + .dev = UART1, + .freq = CLOCK_CORECLOCK, + .pin_rx = GPIO_PIN(PORT_E, 1), + .pin_tx = GPIO_PIN(PORT_E, 0), + .pcr_rx = PORT_PCR_MUX(3), + .pcr_tx = PORT_PCR_MUX(3), + .irqn = UART1_RX_TX_IRQn, + .scgc_addr = &SIM_SCGC4, + .scgc_bit = SIM_SCGC4_UART1_SHIFT, + .mode = UART_MODE_8N1, + }, +}; + +#define UART_0_ISR (isr_uart1_rx_tx) + +#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) +/** @} */ + +/** + * @name ADC configuration + * @{ + */ +static const adc_conf_t adc_config[] = { + /* dev, pin, channel */ + { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC0_DP0 */ + { .dev = ADC0, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC0_DM0 */ + { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 0 }, /* ADC1_DP0 */ + { .dev = ADC1, .pin = GPIO_UNDEF , .chan = 19 }, /* ADC1_DM0 */ + { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, /* PTB0 (Arduino A0) */ + { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, /* PTB1 (Arduino A1) */ + { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15 }, /* PTC1 (Arduino A2) */ + { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 4 }, /* PTC2 (Arduino A3) */ +}; + +#define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0])) +/** @} */ + +/** + * @name DAC configuration + * @{ + */ +#define DAC_CONFIG {} +#define DAC_NUMOF 0 +/** @} */ + +/** + * @name PWM configuration + * @{ + */ +static const pwm_conf_t pwm_config[] = { + { + .ftm = FTM0, + .chan = { + { .pin = GPIO_PIN(PORT_A, 1), .af = 3, .ftm_chan = 6 }, + { .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 }, + { .pin = GPIO_PIN(PORT_D, 5), .af = 4, .ftm_chan = 5 }, + }, + .chan_numof = 3, + .ftm_num = 0 + } +}; + +#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) +/** @} */ + + +/** + * @name SPI configuration + * + * Clock configuration values based on the configured 48Mhz module clock. + * + * Auto-generated by: + * cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c + * +* @{ +*/ +static const uint32_t spi_clk_config[] = { + ( + SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | /* -> 93750Hz */ + SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(8) | + SPI_CTAR_PASC(0) | SPI_CTAR_ASC(8) | + SPI_CTAR_PDT(0) | SPI_CTAR_DT(8) + ), + ( + SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | /* -> 375000Hz */ + SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(6) | + SPI_CTAR_PASC(0) | SPI_CTAR_ASC(6) | + SPI_CTAR_PDT(0) | SPI_CTAR_DT(6) + ), + ( + SPI_CTAR_PBR(1) | SPI_CTAR_BR(4) | /* -> 1000000Hz */ + SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(3) | + SPI_CTAR_PASC(1) | SPI_CTAR_ASC(3) | + SPI_CTAR_PDT(1) | SPI_CTAR_DT(3) + ), + ( + SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | /* -> 4800000Hz */ + SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(0) | + SPI_CTAR_PASC(2) | SPI_CTAR_ASC(0) | + SPI_CTAR_PDT(2) | SPI_CTAR_DT(0) + ), + ( + SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 8000000Hz */ + SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) | + SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) | + SPI_CTAR_PDT(1) | SPI_CTAR_DT(0) + ) +}; + +static const spi_conf_t spi_config[] = { + { + .dev = SPI0, + .pin_miso = GPIO_PIN(PORT_D, 3), + .pin_mosi = GPIO_PIN(PORT_D, 2), + .pin_clk = GPIO_PIN(PORT_D, 1), + .pin_cs = { + GPIO_PIN(PORT_C, 4), + GPIO_PIN(PORT_D, 4), + GPIO_UNDEF, + GPIO_UNDEF, + GPIO_UNDEF + }, + .pcr = GPIO_AF_2, + .simmask = SIM_SCGC6_SPI0_MASK + } +}; + +#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) +/** @} */ + + +/** +* @name I2C configuration +* @{ +*/ +#define I2C_NUMOF (1U) +#define I2C_CLK CLOCK_CORECLOCK +#define I2C_0_EN 1 +#define I2C_IRQ_PRIO 1 +/* Low (10 kHz): MUL = 4, SCL divider = 1280, total: 5120 */ +#define KINETIS_I2C_F_ICR_LOW (0x35) +#define KINETIS_I2C_F_MULT_LOW (2) +/* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */ +#define KINETIS_I2C_F_ICR_NORMAL (0x1F) +#define KINETIS_I2C_F_MULT_NORMAL (1) +/* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */ +#define KINETIS_I2C_F_ICR_FAST (0x17) +#define KINETIS_I2C_F_MULT_FAST (0) +/* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */ +#define KINETIS_I2C_F_ICR_FAST_PLUS (0x10) +#define KINETIS_I2C_F_MULT_FAST_PLUS (0) + +/* I2C 0 device configuration */ +#define I2C_0_DEV I2C0 +#define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK)) +#define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK)) +#define I2C_0_IRQ I2C0_IRQn +#define I2C_0_IRQ_HANDLER isr_i2c0 +/* I2C 0 pin configuration */ +#define I2C_0_PORT PORTB +#define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK)) +#define I2C_0_PIN_AF 2 +#define I2C_0_SDA_PIN 3 +#define I2C_0_SCL_PIN 2 +#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK) +/** @} */ + +/** + * @name GPIO configuration + * @{ + */ +#define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO +/** @} */ + +/** +* @name RTT and RTC configuration +* @{ +*/ +#define RTT_NUMOF (1U) +#define RTC_NUMOF (1U) +#define RTT_DEV RTC +#define RTT_IRQ RTC_IRQn +#define RTT_IRQ_PRIO 10 +#define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK)) +#define RTT_ISR isr_rtc +#define RTT_FREQUENCY (1) +#define RTT_MAX_VALUE (0xffffffff) +/** @} */ + +/** + * @name Random Number Generator configuration + * @{ + */ +#define KINETIS_RNGA RNG +#define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9)) +#define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9)) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */