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Merge pull request #6708 from haukepetersen/rm_msp_flashrom

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cpu/msp430: added flashpage implementation
This commit is contained in:
Francisco Acosta 2017-08-29 13:11:56 +02:00 committed by GitHub
commit 8816a3e8c5
11 changed files with 91 additions and 187 deletions
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3
boards/msb-430/Makefile.features
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@ -1,7 +1,8 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# Various other features (if any)

1
boards/msb-430h/Makefile.features
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@ -1,5 +1,6 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

1
boards/telosb/Makefile.features
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@ -1,4 +1,5 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer

1
boards/wsn430-v1_3b/Makefile.features
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@ -1,4 +1,5 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_spi

1
boards/wsn430-v1_4/Makefile.features
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@ -1,4 +1,5 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_spi

1
boards/z1/Makefile.features
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@ -1,4 +1,5 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer

74
cpu/cc430/flashrom.c
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@ -1,74 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cc430
* @{
*/
/**
* @file
* @brief cc430 flashrom driver
*
* @author Kévin Roussel <Kevin.Roussel@inria.fr>
*/
#include <stddef.h>
#include <stdint.h>
#include "cpu.h"
#include "irq.h"
static inline uint8_t prepare(void);
static inline void finish(uint8_t istate);
static inline void busy_wait(void);
/**
* @TODO implement this function
*/
uint8_t flashrom_erase(uint8_t *addr)
{
(void) addr;
return 0;
}
/**
* @TODO implement this function
*/
uint8_t flashrom_write(uint8_t *dst, const uint8_t *src, size_t size)
{
(void) dst;
(void) src;
(void) size;
return 0;
}
/**
* @TODO implement this function
*/
static inline uint8_t prepare(void)
{
return 0;
}
/**
* @TODO implement this function
*/
static inline void finish(uint8_t istate)
{
(void) istate;
}
static inline void busy_wait(void)
{
/* Wait for BUSY = 0, not needed unless run from RAM */
while (FCTL3 & 0x0001) {
nop();
}
}

6
cpu/msp430_common/Makefile.include
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@ -1,7 +1,11 @@
INCLUDES += -I$(RIOTCPU)/msp430_common/include/
# export the CPU model
MODEL = $(shell echo $(CPU_MODEL) | tr 'a-z' 'A-Z')
export CFLAGS += -DCPU_MODEL_$(MODEL)
export UNDEF += $(BINDIR)/msp430_common/startup.o
export USEMODULE += msp430_common msp430_common_periph
export USEMODULE += msp430_common msp430_common_periph periph_common
DEFAULT_MODULE += oneway_malloc

23
cpu/msp430_common/include/cpu_conf.h
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@ -14,7 +14,28 @@ extern "C" {
#endif
/**
* @name Kernel configuration
* @name Configure the internal flash memory
* @{
*/
#define FLASHPAGE_SIZE (512)
#if defined (CPU_MODEL_MSP430F1611)
#define CPU_FLASH_BASE (0x4000)
#define FLASHPAGE_NUMOF (96) /* 48K */
#elif defined (CPU_MODEL_MSP430F1612)
#define CPU_FLASH_BASE (0x2600)
#define FLASHPAGE_NUMOF (110) /* 56K */
#elif defined (CPU_MODEL_MSP430F2617)
#define CPU_FLASH_BASE (0x3100)
#define FLASHPAGE_NUMOF (128) /* we can currently only access 52K */
#elif defined (CPU_MODEL_CC430F6137)
#define CPU_FLASH_BASE (0x8000)
#define FLASHPAGE_NUMOF (64) /* 32K */
#endif
/** @} */
/**
* @name Kernel configuration
* @{
*/
#ifndef THREAD_EXTRA_STACKSIZE_PRINTF

57
cpu/msp430_common/periph/flashpage.c Normal file
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@ -0,0 +1,57 @@
/*
* Copyright (C) 2014 INRIA
* 2017 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_msp430fxyz
* @{
*
* @file
* @brief Implementation of the peripheral flashpage interface
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
#include "cpu.h"
#include "irq.h"
#include "periph/flashpage.h"
void flashpage_write(int page, void *data)
{
assert(page < FLASHPAGE_NUMOF);
uint8_t *src = (uint8_t *)data;
uint8_t *dst = (uint8_t *)flashpage_addr(page);
unsigned istate;
/* disable interrupts and unlock flash */
istate = irq_disable();
FCTL3 = FWKEY;
while (FCTL3 & BUSY) {}
/* erase page */
FCTL1 = (FWKEY | ERASE);
*dst = 0; /* erases the page */
while (FCTL3 & BUSY) {}
if (data) {
FCTL1 = (FWKEY | WRT);
for (unsigned i = 0; i < FLASHPAGE_SIZE; i++) {
*(dst++) = *(src++);
while (!(FCTL3 & WAIT)) {}
}
}
/* lock flash and re-enable interrupts */
FCTL1 = (FWKEY);
FCTL3 = (FWKEY | LOCK);
irq_restore(istate);
}

110
cpu/msp430fxyz/flashrom.c
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@ -1,110 +0,0 @@
/*
* Copyright (C) 2014 INRIA
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu
* @{
*
* @file
* @brief MSP430Fxyz flashrom functions
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
*
* @}
*/
#include "irq.h"
#include <stddef.h>
#include <stdint.h>
#include "cpu.h"
#include "irq.h"
uint8_t ie1, ie2;
static uint8_t prepare(void);
static void finish(uint8_t istate);
static inline void busy_wait(void);
/*---------------------------------------------------------------------------*/
uint8_t flashrom_erase(uint8_t *addr)
{
uint8_t istate = prepare();
FCTL3 = FWKEY; /* Lock = 0 */
busy_wait();
FCTL1 = FWKEY | ERASE;
*addr = 0; /* erase Flash segment */
busy_wait();
FCTL1 = FWKEY; /* ERASE = 0 */
FCTL3 = FWKEY | LOCK;
finish(istate);
return 1;
}
uint8_t flashrom_write(uint8_t *dst, const uint8_t *src, size_t size)
{
unsigned int i;
FCTL3 = FWKEY; /* Lock = 0 */
busy_wait();
for (i = size; i > 0; i--) {
FCTL1 = FWKEY | WRT;
*(dst++) = *(src++); /* program Flash word */
while (!(FCTL3 & WAIT)) {
nop();
}
}
busy_wait();
FCTL1 = FWKEY; /* WRT = 0 */
FCTL3 = FWKEY | LOCK; /* Lock = 1 */
return 1;
}
/*---------------------------------------------------------------------------*/
static uint8_t prepare(void)
{
uint8_t istate;
/* Disable all interrupts. */
/* Clear interrupt flag1. */
IFG1 = 0;
/* DCO(SMCLK) is 2,4576MHz, /6 = 409600 Hz
select SMCLK for flash timing, divider 4+1 */
FCTL2 = FWKEY | FSSEL_3 | FN2 | FN0;
/* disable all interrupts to protect CPU
during programming from system crash */
istate = irq_disable();
/* disable all NMI-Interrupt sources */
ie1 = IE1;
ie2 = IE2;
IE1 = 0x00;
IE2 = 0x00;
return istate;
}
/*---------------------------------------------------------------------------*/
void finish(uint8_t istate)
{
/* Enable interrupts. */
IE1 = ie1;
IE2 = ie2;
irq_restore(istate);
}
static inline void busy_wait(void)
{
/* Wait for BUSY = 0, not needed unless run from RAM */
while (FCTL3 & 0x0001) {
nop();
}
}