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boards: use SAM0_GCLK_TIMER for saml21 boards

This commit is contained in:
Antonio Galea 2021-05-05 10:56:58 +02:00
parent 8bd90aaf00
commit 7a253b4b76
5 changed files with 7 additions and 7 deletions

View File

@ -48,7 +48,7 @@ static const tc32_conf_t timer_config[] = {
.mclk = &MCLK->APBCMASK.reg,
.mclk_mask = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
.gclk_id = TC0_GCLK_ID,
.gclk_src = SAM0_GCLK_8MHZ,
.gclk_src = SAM0_GCLK_TIMER,
.flags = TC_CTRLA_MODE_COUNT32,
}
};

View File

@ -51,7 +51,7 @@ static const tc32_conf_t timer_config[] = {
.mclk = &MCLK->APBCMASK.reg,
.mclk_mask = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
.gclk_id = TC0_GCLK_ID,
.gclk_src = SAM0_GCLK_8MHZ,
.gclk_src = SAM0_GCLK_TIMER,
.flags = TC_CTRLA_MODE_COUNT32,
}
};
@ -124,7 +124,7 @@ static const pwm_conf_t pwm_config[] = {
{ .tim = TCC_CONFIG(TCC0),
.chan = pwm_chan0_config,
.chan_numof = ARRAY_SIZE(pwm_chan0_config),
.gclk_src = SAM0_GCLK_8MHZ,
.gclk_src = SAM0_GCLK_TIMER,
},
#endif
};
@ -222,7 +222,7 @@ static const adc_conf_chan_t adc_channels[] = {
* @{
*/
/* Must not exceed 12 MHz */
#define DAC_CLOCK SAM0_GCLK_8MHZ
#define DAC_CLOCK SAM0_GCLK_TIMER
/* use Vcc as reference voltage */
#define DAC_VREF DAC_CTRLB_REFSEL_VDDANA
/** @} */

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@ -41,7 +41,7 @@ static const tc32_conf_t timer_config[] = {
.mclk = &MCLK->APBCMASK.reg,
.mclk_mask = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
.gclk_id = TC0_GCLK_ID,
.gclk_src = SAM0_GCLK_8MHZ,
.gclk_src = SAM0_GCLK_TIMER,
.flags = TC_CTRLA_MODE_COUNT32,
}
};

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@ -48,7 +48,7 @@ static const tc32_conf_t timer_config[] = {
.mclk = &MCLK->APBCMASK.reg,
.mclk_mask = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
.gclk_id = TC0_GCLK_ID,
.gclk_src = SAM0_GCLK_8MHZ,
.gclk_src = SAM0_GCLK_TIMER,
.flags = TC_CTRLA_MODE_COUNT32,
}
};

View File

@ -48,7 +48,7 @@ static const tc32_conf_t timer_config[] = {
.mclk = &MCLK->APBCMASK.reg,
.mclk_mask = MCLK_APBCMASK_TC0 | MCLK_APBCMASK_TC1,
.gclk_id = TC0_GCLK_ID,
.gclk_src = SAM0_GCLK_8MHZ,
.gclk_src = SAM0_GCLK_TIMER,
.flags = TC_CTRLA_MODE_COUNT32,
}
};