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cpu/sam0: use generic hw fc module
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@ -31,7 +31,4 @@ CFLAGS += -DDONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
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# For Cortex-M cpu we use the common cortexm.ld linker script
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# For Cortex-M cpu we use the common cortexm.ld linker script
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LINKER_SCRIPT ?= cortexm.ld
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LINKER_SCRIPT ?= cortexm.ld
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# define sam0 specific pseudomodules
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PSEUDOMODULES += sam0_periph_uart_hw_fc
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INCLUDES += -I$(RIOTCPU)/sam0_common/include
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INCLUDES += -I$(RIOTCPU)/sam0_common/include
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@ -212,7 +212,7 @@ typedef struct {
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SercomUsart *dev; /**< pointer to the used UART device */
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SercomUsart *dev; /**< pointer to the used UART device */
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gpio_t rx_pin; /**< pin used for RX */
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gpio_t rx_pin; /**< pin used for RX */
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gpio_t tx_pin; /**< pin used for TX */
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gpio_t tx_pin; /**< pin used for TX */
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#ifdef MODULE_SAM0_PERIPH_UART_HW_FC
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#ifdef MODULE_PERIPH_UART_HW_FC
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gpio_t rts_pin; /**< pin used for RTS */
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gpio_t rts_pin; /**< pin used for RTS */
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gpio_t cts_pin; /**< pin used for CTS */
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gpio_t cts_pin; /**< pin used for CTS */
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#endif
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#endif
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@ -80,7 +80,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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gpio_set(uart_config[uart].tx_pin);
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gpio_set(uart_config[uart].tx_pin);
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gpio_init_mux(uart_config[uart].tx_pin, uart_config[uart].mux);
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gpio_init_mux(uart_config[uart].tx_pin, uart_config[uart].mux);
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#ifdef MODULE_SAM0_PERIPH_UART_HW_FC
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#ifdef MODULE_PERIPH_UART_HW_FC
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/* If RTS/CTS needed, enable them */
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/* If RTS/CTS needed, enable them */
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if (uart_config[uart].tx_pad == UART_PAD_TX_0_RTS_2_CTS_3) {
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if (uart_config[uart].tx_pad == UART_PAD_TX_0_RTS_2_CTS_3) {
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/* Ensure RTS is defined */
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/* Ensure RTS is defined */
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