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boards/stm32l0: set LSE to 0 default, override in boards

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This commit is contained in:
Alexandre Abadie 2020-08-28 20:17:47 +02:00
parent 23117a844e
commit 67a1c029b4
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GPG Key ID: 1C919A403CAE1405
8 changed files with 31 additions and 26 deletions
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5
boards/b-l072z-lrwan1/include/periph_conf.h
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@ -19,6 +19,11 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "cfg_rtt_default.h"

2
boards/common/stm32/include/l0/cfg_clock_default.h
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@ -87,7 +87,7 @@ extern "C" {
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE (0)
#endif
#if CONFIG_BOARD_HAS_LSE
#define CLOCK_LSE (1)

5
boards/i-nucleo-lrwan1/include/periph_conf.h
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@ -19,6 +19,11 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "cfg_rtt_default.h"

5
boards/lsn50/include/periph_conf.h
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@ -19,6 +19,11 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "cfg_rtt_default.h"

5
boards/nucleo-l031k6/include/periph_conf.h
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@ -21,6 +21,11 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "cfg_i2c1_pb6_pb7.h"

5
boards/nucleo-l053r8/include/periph_conf.h
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@ -21,6 +21,11 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "cfg_rtt_default.h"

5
boards/nucleo-l073rz/include/periph_conf.h
View File

@ -21,6 +21,11 @@
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "cfg_rtt_default.h"

25
boards/stm32l0538-disco/include/periph_conf.h
View File

@ -26,31 +26,6 @@
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
#define CLOCK_HSI (16000000U) /* internal oscillator */
#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
#define CLOCK_LSE (0) /* enable low speed external oscillator */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/**
* @name Timer configuration
* @{