1
0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00

boards/nucleo-g070rb: add support

This commit is contained in:
Alexandre Abadie 2020-05-05 11:12:34 +02:00
parent 8272541b44
commit 54fe59d0ba
No known key found for this signature in database
GPG Key ID: 1C919A403CAE1405
7 changed files with 183 additions and 0 deletions

View File

@ -0,0 +1,26 @@
# Copyright (c) 2020 Inria
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config BOARD
default "nucleo-g070rb" if BOARD_NUCLEO_G070RB
config BOARD_NUCLEO_G070RB
bool
default y
select BOARD_COMMON_NUCLEO64
select CPU_MODEL_STM32G070RB
# Put defined MCU peripherals here (in alphabetical order)
select HAS_PERIPH_I2C
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
# Put other features for this board (in alphabetical order)
select HAS_RIOTBOOT
source "$(RIOTBOARD)/common/nucleo64/Kconfig"

View File

@ -0,0 +1,4 @@
MODULE = board
DIRS = $(RIOTBOARD)/common/nucleo
include $(RIOTBASE)/Makefile.base

View File

@ -0,0 +1 @@
include $(RIOTBOARD)/common/nucleo/Makefile.dep

View File

@ -0,0 +1,14 @@
CPU = stm32
CPU_MODEL = stm32g070rb
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# Put other features for this board (in alphabetical order)
FEATURES_PROVIDED += riotboot
# load the common Makefile.features for Nucleo boards
include $(RIOTBOARD)/common/nucleo64/Makefile.features

View File

@ -0,0 +1,2 @@
# load the common Makefile.include for Nucleo boards
include $(RIOTBOARD)/common/nucleo64/Makefile.include

View File

@ -0,0 +1,5 @@
/**
@defgroup boards_nucleo-g070rb STM32 Nucleo-G070RB
@ingroup boards_common_nucleo64
@brief Support for the STM32 Nucleo-G070RB
*/

View File

@ -0,0 +1,131 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo-g070rb
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo-g070rb board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "g0/cfg_clock_default.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM3,
.max = 0x0000ffff,
.rcc_mask = RCC_APBENR1_TIM3EN,
.bus = APB1,
.irqn = TIM3_IRQn
}
};
#define TIMER_0_ISR isr_tim3
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rcc_mask = RCC_APBENR1_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF1,
.tx_af = GPIO_AF1,
.bus = APB1,
.irqn = USART2_IRQn,
},
{ /* Arduino pinout on D0/D1 */
.dev = USART1,
.rcc_mask = RCC_APBENR2_USART1EN,
.rx_pin = GPIO_PIN(PORT_C, 5),
.tx_pin = GPIO_PIN(PORT_C, 4),
.rx_af = GPIO_AF1,
.tx_af = GPIO_AF1,
.bus = APB12,
.irqn = USART1_IRQn,
},
};
#define UART_0_ISR (isr_usart2)
#define UART_1_ISR (isr_usart1)
#define UART_NUMOF ARRAY_SIZE(uart_config)
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for 64000000Hz */
7, /* -> 250000Hz */
6, /* -> 500000Hz */
5, /* -> 1000000Hz */
3, /* -> 4000000Hz */
2 /* -> 8000000Hz */
},
{ /* for 64000000Hz */
7, /* -> 250000Hz */
6, /* -> 500000Hz */
5, /* -> 1000000Hz */
3, /* -> 4000000Hz */
2 /* -> 8000000Hz */
},
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7), /* Arduino D11 */
.miso_pin = GPIO_PIN(PORT_A, 6), /* Arduino D12 */
.sclk_pin = GPIO_PIN(PORT_A, 5), /* Arduino D13 */
.cs_pin = GPIO_UNDEF,
.mosi_af = GPIO_AF0,
.miso_af = GPIO_AF0,
.sclk_af = GPIO_AF0,
.cs_af = GPIO_AF0,
.rccmask = RCC_APBENR2_SPI1EN,
.apbbus = APB12,
},
};
#define SPI_NUMOF ARRAY_SIZE(spi_config)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */