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boards/nucleo-g070rb: add support
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26
boards/nucleo-g070rb/Kconfig
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26
boards/nucleo-g070rb/Kconfig
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# Copyright (c) 2020 Inria
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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config BOARD
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default "nucleo-g070rb" if BOARD_NUCLEO_G070RB
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config BOARD_NUCLEO_G070RB
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bool
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default y
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select BOARD_COMMON_NUCLEO64
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select CPU_MODEL_STM32G070RB
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# Put defined MCU peripherals here (in alphabetical order)
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select HAS_PERIPH_I2C
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select HAS_PERIPH_SPI
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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# Put other features for this board (in alphabetical order)
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select HAS_RIOTBOOT
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source "$(RIOTBOARD)/common/nucleo64/Kconfig"
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4
boards/nucleo-g070rb/Makefile
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4
boards/nucleo-g070rb/Makefile
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MODULE = board
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DIRS = $(RIOTBOARD)/common/nucleo
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include $(RIOTBASE)/Makefile.base
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1
boards/nucleo-g070rb/Makefile.dep
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1
boards/nucleo-g070rb/Makefile.dep
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include $(RIOTBOARD)/common/nucleo/Makefile.dep
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14
boards/nucleo-g070rb/Makefile.features
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14
boards/nucleo-g070rb/Makefile.features
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CPU = stm32
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CPU_MODEL = stm32g070rb
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Put other features for this board (in alphabetical order)
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FEATURES_PROVIDED += riotboot
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# load the common Makefile.features for Nucleo boards
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include $(RIOTBOARD)/common/nucleo64/Makefile.features
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2
boards/nucleo-g070rb/Makefile.include
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2
boards/nucleo-g070rb/Makefile.include
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# load the common Makefile.include for Nucleo boards
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include $(RIOTBOARD)/common/nucleo64/Makefile.include
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5
boards/nucleo-g070rb/doc.txt
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5
boards/nucleo-g070rb/doc.txt
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/**
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@defgroup boards_nucleo-g070rb STM32 Nucleo-G070RB
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@ingroup boards_common_nucleo64
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@brief Support for the STM32 Nucleo-G070RB
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*/
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131
boards/nucleo-g070rb/include/periph_conf.h
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131
boards/nucleo-g070rb/include/periph_conf.h
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/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-g070rb
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-g070rb board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "g0/cfg_clock_default.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_rtt_default.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM3,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APBENR1_TIM3EN,
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.bus = APB1,
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.irqn = TIM3_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim3
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APBENR1_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF1,
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.tx_af = GPIO_AF1,
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.bus = APB1,
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.irqn = USART2_IRQn,
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},
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{ /* Arduino pinout on D0/D1 */
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.dev = USART1,
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.rcc_mask = RCC_APBENR2_USART1EN,
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.rx_pin = GPIO_PIN(PORT_C, 5),
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.tx_pin = GPIO_PIN(PORT_C, 4),
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.rx_af = GPIO_AF1,
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.tx_af = GPIO_AF1,
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.bus = APB12,
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.irqn = USART1_IRQn,
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},
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_1_ISR (isr_usart1)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for 64000000Hz */
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7, /* -> 250000Hz */
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6, /* -> 500000Hz */
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5, /* -> 1000000Hz */
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3, /* -> 4000000Hz */
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2 /* -> 8000000Hz */
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},
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{ /* for 64000000Hz */
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7, /* -> 250000Hz */
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6, /* -> 500000Hz */
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5, /* -> 1000000Hz */
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3, /* -> 4000000Hz */
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2 /* -> 8000000Hz */
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},
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7), /* Arduino D11 */
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.miso_pin = GPIO_PIN(PORT_A, 6), /* Arduino D12 */
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.sclk_pin = GPIO_PIN(PORT_A, 5), /* Arduino D13 */
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF0,
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.miso_af = GPIO_AF0,
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.sclk_af = GPIO_AF0,
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.cs_af = GPIO_AF0,
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.rccmask = RCC_APBENR2_SPI1EN,
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.apbbus = APB12,
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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