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boards/common/stm32: add common code for stm32g0

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This commit is contained in:
Alexandre Abadie 2020-05-04 12:36:40 +02:00
parent fc1d642113
commit 8272541b44
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GPG Key ID: 1C919A403CAE1405
4 changed files with 94 additions and 1 deletions
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4
boards/common/nucleo/include/board_nucleo.h
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@ -37,6 +37,10 @@ extern "C" {
#define XTIMER_WIDTH (16)
#endif
#if defined(CPU_FAM_STM32G0)
#define XTIMER_WIDTH (16)
#endif
#if defined(CPU_FAM_STM32F1)
#define XTIMER_WIDTH (16)
#define XTIMER_BACKOFF (19)

3
boards/common/stm32/dist/stm32g0.cfg vendored Normal file
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@ -0,0 +1,3 @@
source [find target/stm32g0x.cfg]
reset_config srst_only
$_TARGETNAME configure -rtos auto

8
boards/common/stm32/include/cfg_i2c1_pb8_pb9.h
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@ -38,6 +38,9 @@ static const i2c_conf_t i2c_config[] = {
#if CPU_FAM_STM32F0
.scl_af = GPIO_AF1,
.sda_af = GPIO_AF1,
#elif CPU_FAM_STM32G0
.scl_af = GPIO_AF6,
.sda_af = GPIO_AF6,
#else
.scl_af = GPIO_AF4,
.sda_af = GPIO_AF4,
@ -50,6 +53,9 @@ static const i2c_conf_t i2c_config[] = {
#elif CPU_FAM_STM32L4 || CPU_FAM_STM32WB || CPU_FAM_STM32G4
.rcc_mask = RCC_APB1ENR1_I2C1EN,
.irqn = I2C1_ER_IRQn,
#elif CPU_FAM_STM32G0
.rcc_mask = RCC_APBENR1_I2C1EN,
.irqn = I2C1_IRQn,
#elif CPU_FAM_STM32F7
.rcc_mask = RCC_APB1ENR_I2C1EN,
.irqn = I2C1_ER_IRQn,
@ -67,7 +73,7 @@ static const i2c_conf_t i2c_config[] = {
#define I2C_0_ISR isr_i2c1_ev
#elif CPU_FAM_STM32L4 || CPU_FAM_STM32F7 || CPU_FAM_STM32WB
#define I2C_0_ISR isr_i2c1_er
#elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0
#elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0 || CPU_FAM_STM32G0
#define I2C_0_ISR isr_i2c1
#endif

80
boards/common/stm32/include/g0/cfg_clock_default.h Normal file
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@ -0,0 +1,80 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32G0 clock
*
* CORECLOCK cannot exceeds 64MHz core clock. LSE is 32768Hz.
* Default configuration use PLL clock as system clock. PLL input clock is HSI
* by default.
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef G0_CFG_CLOCK_DEFAULT_H
#define G0_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
#define CLOCK_USE_HSI (0)
#define CLOCK_USE_HSE (0)
#define CLOCK_USE_PLL (1)
#define CLOCK_HSI (16000000U)
#ifndef CLOCK_HSE
#define CLOCK_HSE (0)
#endif
#ifndef CLOCK_LSE
#define CLOCK_LSE (1U)
#endif
#if CLOCK_USE_HSI
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif CLOCK_USE_HSE
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif CLOCK_USE_PLL
/* The following parameters configure a 64MHz system clock with HSI as input clock */
#define CLOCK_PLL_M (1)
#define CLOCK_PLL_N (20)
#define CLOCK_PLL_R (5)
#if CLOCK_HSE
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_R
#endif /* CLOCK_USE_PLL */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_0
#define CLOCK_AHB (CLOCK_CORECLOCK / 1) /* max: 64MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE_0
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) /* max: 64MHz */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* G0_CFG_CLOCK_DEFAULT_H */
/** @} */