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cpu/atxmega/atxmega_cpu: Fix clk sel after dfll en

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The current ATxmega clock_init enable DFLL to improve the accuracy of
the 2MHz and 32MHz internal oscillators.  In some ATxmega revisions,
after started DFLL the clock become unstable.  Add another sync point
for 32MHz internal oscilator.

Note:  If clock is not stable, system won't switch from 2MHz to 32MHz
as main clock.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2021-03-28 11:40:36 -03:00
parent 80e14e88a1
commit 53235dd2e2
1 changed files with 7 additions and 2 deletions
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9
cpu/atxmega/atxmega_cpu.c
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@ -98,10 +98,15 @@ void __attribute__((weak)) avr8_clk_init(void)
!= (OSC_RC32KRDY_bm | OSC_RC32MRDY_bm)) {}
/* Enable DFLL - defaults to calibrate against internal 32Khz clock */
DFLLRC32M.CTRL = DFLL_ENABLE_bm;
DFLLRC2M.CTRL = DFLL_ENABLE_bm;
/* Enable DFLL - defaults to calibrate against internal 32Khz clock */
DFLLRC2M.CTRL = DFLL_ENABLE_bm;
DFLLRC32M.CTRL = DFLL_ENABLE_bm;
/* Some ATxmega need sync clocks after enable DFLL. Otherwise clock may
* stay at 2MHz source when try enable.
*/
while ((OSC.STATUS & OSC_RC32MRDY_bm) != OSC_RC32MRDY_bm) {}
atxmega_set_prescaler(CPU_ATXMEGA_CLK_SCALE_INIT,
CPU_ATXMEGA_BUS_SCALE_INIT);