Merge pull request #18644 from gschorcht/drivers/synopsys_dwc2

drivers: add driver for Synopsys DWC2 that is used as USB OTG peripheral on STM32 and ESP32x SoCs

boards/common/esp32s2/include/periph_conf_common.h

@@ -337,6 +337,31 @@ static const uart_conf_t uart_config[] = {
 #define UART_NUMOF  ARRAY_SIZE(uart_config)
 /** @} */
 
+/**
+ * @name   USB device configuration
+ *
+ * @{
+ */
+
+#include "usbdev_esp32.h"
+
+/**
+ * @brief   Static array with USB OTG FS configuration
+ */
+static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = {
+    {
+        .periph = USB_OTG_FS_PERIPH_BASE,
+        .type = DWC2_USB_OTG_FS,
+    }
+};
+
+/**
+ * @brief Number of USB OTG FS interfaces
+ */
+#define USBDEV_NUMOF    ARRAY_SIZE(dwc2_usb_otg_fshs_config)
+
+/** @} */
+
 #ifdef __cplusplus
 } /* end extern "C" */
 #endif

boards/common/esp32s3/include/periph_conf_common.h

@@ -337,6 +337,31 @@ static const uart_conf_t uart_config[] = {
 #define UART_NUMOF  ARRAY_SIZE(uart_config)
 /** @} */
 
+/**
+ * @name   USB device configuration
+ *
+ * @{
+ */
+
+#include "usbdev_esp32.h"
+
+/**
+ * @brief   Static array with USB OTG FS configuration
+ */
+static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = {
+    {
+        .periph = USB_OTG_FS_PERIPH_BASE,
+        .type = DWC2_USB_OTG_FS,
+    }
+};
+
+/**
+ * @brief Number of USB OTG FS interfaces
+ */
+#define USBDEV_NUMOF    ARRAY_SIZE(dwc2_usb_otg_fshs_config)
+
+/** @} */
+
 #ifdef __cplusplus
 } /* end extern "C" */
 #endif

boards/common/stm32/include/cfg_usb_otg_fs.h

@@ -20,6 +20,7 @@
 #define CFG_USB_OTG_FS_H
 
 #include "periph_cpu.h"
+#include "usbdev_synopsys_dwc2.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -28,18 +29,17 @@ extern "C" {
 /**
  * @brief Enable the full speed USB OTG peripheral
  */
-#define STM32_USB_OTG_FS_ENABLED
+#define DWC2_USB_OTG_FS_ENABLED
 
 /**
- * @name common USB OTG FS configuration
- * @{
+ * @brief Common USB OTG FS configuration
  */
-static const stm32_usb_otg_fshs_config_t stm32_usb_otg_fshs_config[] = {
+static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = {
     {
         .periph   = USB_OTG_FS_PERIPH_BASE,
+        .type     = DWC2_USB_OTG_FS,
+        .phy      = DWC2_USB_OTG_PHY_BUILTIN,
         .rcc_mask = RCC_AHB2ENR_OTGFSEN,
-        .phy      = STM32_USB_OTG_PHY_BUILTIN,
-        .type     = STM32_USB_OTG_FS,
         .irqn     = OTG_FS_IRQn,
         .ahb      = AHB2,
         .dm       = GPIO_PIN(PORT_A, 11),
@@ -47,12 +47,11 @@ static const stm32_usb_otg_fshs_config_t stm32_usb_otg_fshs_config[] = {
         .af       = GPIO_AF10,
     }
 };
-/** @} */
 
 /**
  * @brief Number of available USB OTG peripherals
  */
-#define USBDEV_NUMOF           ARRAY_SIZE(stm32_usb_otg_fshs_config)
+#define USBDEV_NUMOF           ARRAY_SIZE(dwc2_usb_otg_fshs_config)
 
 #ifdef __cplusplus
 }

boards/common/stm32/include/cfg_usb_otg_hs_fs.h

@@ -20,6 +20,7 @@
 #define CFG_USB_OTG_HS_FS_H
 
 #include "periph_cpu.h"
+#include "usbdev_synopsys_dwc2.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -28,18 +29,17 @@ extern "C" {
 /**
  * @brief Enable the full speed USB OTG peripheral
  */
-#define STM32_USB_OTG_HS_ENABLED
+#define DWC2_USB_OTG_HS_ENABLED
 
 /**
- * @name common USB OTG FS configuration
- * @{
+ * @brief Common USB OTG FS configuration
  */
-static const stm32_usb_otg_fshs_config_t stm32_usb_otg_fshs_config[] = {
+static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = {
     {
         .periph   = USB_OTG_HS_PERIPH_BASE,
+        .type     = DWC2_USB_OTG_HS,
+        .phy      = DWC2_USB_OTG_PHY_BUILTIN,
         .rcc_mask = RCC_AHB1ENR_OTGHSEN,
-        .phy      = STM32_USB_OTG_PHY_BUILTIN,
-        .type     = STM32_USB_OTG_HS,
         .irqn     = OTG_HS_IRQn,
         .ahb      = AHB1,
         .dm       = GPIO_PIN(PORT_B, 14),
@@ -47,12 +47,11 @@ static const stm32_usb_otg_fshs_config_t stm32_usb_otg_fshs_config[] = {
         .af       = GPIO_AF12,
     }
 };
-/** @} */
 
 /**
  * @brief Number of available USB OTG peripherals
  */
-#define USBDEV_NUMOF           ARRAY_SIZE(stm32_usb_otg_fshs_config)
+#define USBDEV_NUMOF           ARRAY_SIZE(dwc2_usb_otg_fshs_config)
 
 #ifdef __cplusplus
 }

boards/esp32s2-devkit/Kconfig

@@ -30,10 +30,14 @@ config BOARD_ESP32S2_DEVKIT
     select HAS_PERIPH_I2C
     select HAS_PERIPH_PWM
     select HAS_PERIPH_SPI
+    select HAS_PERIPH_USBDEV if BOARD_VERSION_ESP32S2_DEVKITC_1
+    select HAS_PERIPH_USBDEV if BOARD_VERSION_ESP32S2_DEVKITC_1U
+    select HAS_PERIPH_USBDEV if BOARD_VERSION_ESP32S2_DEVKITC_1R
+    select HAS_PERIPH_USBDEV if BOARD_VERSION_ESP32S2_DEVKITC_1RU
 
     choice
         bool "ESP32-S2-DevKit board version"
-        default BOARD_VERSION_ESP32S2_DEVKITM_1
+        default BOARD_VERSION_ESP32S2_DEVKITC_1
 
         config BOARD_VERSION_ESP32S2_DEVKITM_1
             bool "ESP32-S2-DevKitM-1"

boards/esp32s2-devkit/Makefile.features

@@ -1,17 +1,17 @@
 # default board version if not defined
-BOARD_VERSION ?= esp32s2-devkitm-1
+BOARD_VERSION ?= esp32s2-devkitc-1
 
 ifeq (esp32s2-devkitm-1,$(BOARD_VERSION))
   CPU_MODEL = esp32s2_mini_1x_n4
 else ifeq (esp32s2-devkitm-1u,$(BOARD_VERSION))
   CPU_MODEL = esp32s2_mini_1x_n4
 else ifeq (esp32s2-devkitm-1r,$(BOARD_VERSION))
-  CPU_MODEL = esp32s2_mini-1x_n4r2
+  CPU_MODEL = esp32s2_mini_1x_n4r2
 else ifeq (esp32s2-devkitm-1ru,$(BOARD_VERSION))
-  CPU_MODEL = esp32s2_mini-1x_n4r2
-else ifeq (esp32s2-devkitc_1,$(BOARD_VERSION))
+  CPU_MODEL = esp32s2_mini_1x_n4r2
+else ifeq (esp32s2-devkitc-1,$(BOARD_VERSION))
   CPU_MODEL = esp32s2_solo_n4
-else ifeq (esp32s2-devkitc_1u,$(BOARD_VERSION))
+else ifeq (esp32s2-devkitc-1u,$(BOARD_VERSION))
   CPU_MODEL = esp32s2_solo_n4
 else ifeq (esp32s2-devkitc-1r,$(BOARD_VERSION))
   CPU_MODEL = esp32s2_solo_n4r2
@@ -40,3 +40,7 @@ FEATURES_PROVIDED += periph_pwm
 FEATURES_PROVIDED += periph_spi
 
 FEATURES_PROVIDED += arduino
+
+ifneq (,$(filter esp32s2-devkitc-%,$(BOARD_VERSION)))
+  FEATURES_PROVIDED += periph_usbdev
+endif

boards/esp32s3-devkit/Kconfig

@@ -43,6 +43,7 @@ config BOARD_ESP32S3_DEVKIT
     select HAS_PERIPH_I2C
     select HAS_PERIPH_PWM
     select HAS_PERIPH_SPI
+    select HAS_PERIPH_USBDEV
 
     choice
         bool "ESP32-S3-DevKit board version"

boards/esp32s3-devkit/Makefile.features

@@ -38,3 +38,4 @@ FEATURES_PROVIDED += periph_spi
 FEATURES_PROVIDED += esp_jtag
 
 FEATURES_PROVIDED += arduino
+FEATURES_PROVIDED += periph_usbdev

cpu/esp32/Kconfig.esp32s2

@@ -25,6 +25,7 @@ config CPU_FAM_ESP32S2
     select MODULE_PS if MODULE_SHELL
     select MODULE_PTHREAD if MODULE_CPP
     select MODULE_RTT_RTC if HAS_PERIPH_RTT && MODULE_PERIPH_RTC
+    select MODULE_USBDEV_SYNOPSYS_DWC2 if HAS_PERIPH_USBDEV && MODULE_PERIPH_USBDEV
     imply MODULE_NEWLIB_NANO
 
 config CPU_FAM

cpu/esp32/Kconfig.esp32s3

@@ -31,6 +31,7 @@ config CPU_FAM_ESP32S3
     select MODULE_PS if MODULE_SHELL
     select MODULE_PTHREAD if MODULE_CPP
     select MODULE_RTT_RTC if HAS_PERIPH_RTT && MODULE_PERIPH_RTC
+    select MODULE_USBDEV_SYNOPSYS_DWC2 if HAS_PERIPH_USBDEV && MODULE_PERIPH_USBDEV
     imply MODULE_NEWLIB_NANO
 
 config CPU_FAM

cpu/esp32/Makefile.dep

@@ -157,6 +157,12 @@ ifneq (,$(filter periph_rtt,$(USEMODULE)))
   USEMODULE += periph_rtt_hw_rtc
 endif
 
+ifneq (,$(filter periph_usbdev,$(USEMODULE)))
+  USEMODULE += esp_idf_usb
+  USEMODULE += usbdev_synopsys_dwc2
+  USEMODULE += ztimer_msec
+endif
+
 ifneq (,$(filter shell,$(USEMODULE)))
   USEMODULE += ps
 endif

cpu/esp32/Makefile.include

@@ -50,6 +50,7 @@ PSEUDOMODULES += esp_wifi_enterprise
 
 INCLUDES += -I$(RIOTCPU)/$(CPU)/esp-idf/include
 INCLUDES += -I$(RIOTCPU)/$(CPU)/esp-idf/include/log
+INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/include
 
 INCLUDES += -I$(ESP32_SDK_DIR)/components
 INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/include
@@ -98,6 +99,10 @@ ifneq (,$(filter esp_idf_spi_flash,$(USEMODULE)))
   INCLUDES += -I$(ESP32_SDK_DIR)/components/spi_flash/include
 endif
 
+ifneq (,$(filter esp_idf_usb,$(USEMODULE)))
+  INCLUDES += -I$(ESP32_SDK_DIR)/components/usb/include
+endif
+
 ifneq (,$(filter esp_wifi_any,$(USEMODULE)))
   INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/include
   INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_eth/include

cpu/esp32/esp-idf/Kconfig

@@ -28,5 +28,6 @@ rsource "heap/Kconfig"
 rsource "nvs_flash/Kconfig"
 rsource "spi_flash/Kconfig"
 rsource "spi_ram/Kconfig"
+rsource "usb/Kconfig"
 rsource "wifi/Kconfig"
 rsource "wpa_supplicant/Kconfig"

cpu/esp32/esp-idf/Makefile

@@ -48,6 +48,10 @@ ifneq (,$(filter esp_idf_spi_ram,$(USEMODULE)))
   DIRS += spi_ram
 endif
 
+ifneq (,$(filter esp_idf_usb,$(USEMODULE)))
+  DIRS += usb
+endif
+
 ifneq (,$(filter esp_idf_wifi,$(USEMODULE)))
   DIRS += wifi
 endif

cpu/esp32/esp-idf/usb/Kconfig

@@ -0,0 +1,14 @@
+# Copyright (c) 2022 Gunar Schorcht
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config MODULE_ESP_IDF_USB
+    bool
+    depends on TEST_KCONFIG
+    depends on MODULE_ESP_IDF
+    default y if MODULE_PERIPH_USBDEV
+    help
+        ESP-IDF code for USB.

cpu/esp32/esp-idf/usb/Makefile

@@ -0,0 +1,17 @@
+MODULE = esp_idf_usb
+
+# source files to be compiled for this module
+ESP32_SDK_SRC = \
+  components/hal/usb_hal.c \
+  components/hal/usb_phy_hal.c \
+  components/soc/$(CPU_FAM)/usb_periph.c \
+  components/soc/$(CPU_FAM)/usb_phy_periph.c \
+  components/usb/usb_phy.c \
+  #
+
+include $(RIOTBASE)/Makefile.base
+
+ESP32_SDK_BIN = $(BINDIR)/$(MODULE)
+
+include ../esp_idf.mk
+include ../esp_idf_cflags.mk

cpu/esp32/include/irq_arch.h

@@ -39,6 +39,7 @@ extern "C" {
 #define CPU_INUM_GPIO       2   /**< Level interrupt with low priority 1 */
 #define CPU_INUM_CAN        3   /**< Level interrupt with low priority 1 */
 #define CPU_INUM_UART       4   /**< Level interrupt with low priority 1 */
+#define CPU_INUM_USB        8   /**< Level interrupt with low priority 1 */
 #define CPU_INUM_RTT        9   /**< Level interrupt with low priority 1 */
 #define CPU_INUM_I2C        12  /**< Level interrupt with low priority 1 */
 #define CPU_INUM_WDT        13  /**< Level interrupt with low priority 1 */

cpu/esp32/include/periph_cpu.h

@@ -811,7 +811,21 @@ typedef struct {
 /**
  * @brief   Maximum number of UART interfaces
  */
-#define UART_NUMOF_MAX  (SOC_UART_NUM)
+#define UART_NUMOF_MAX      (SOC_UART_NUM)
+/** @} */
+
+/**
+ * @name   USB device configuration
+ * @{
+ *
+ * ESP32x SoCs integrate depending on the specific ESP32x SoC variant (family) an USB OTG FS controller based on the Synopsys DWC2 IP core.
+ */
+#include "usbdev_synopsys_dwc2.h"
+
+/**
+ * @brief   Maximum number of USB OTG FS interfaces
+ */
+#define USBDEV_NUMOF_MAX    (SOC_USB_PERIPH_NUM)
 /** @} */
 
 #ifdef __cplusplus

cpu/esp32/include/periph_cpu_esp32c3.h

@@ -167,10 +167,6 @@ extern "C" {
  *
  */
 
-#ifdef MODULE_PERIPH_CAN
-#include "can_esp.h"
-#endif
-
 #ifdef __cplusplus
 }
 #endif

cpu/esp32/include/periph_cpu_esp32s2.h

@@ -212,13 +212,69 @@ extern "C" {
  * UART_DEV(2) | RxD  | -      |`UART2_RXD` | optional, can be overridden (no direct I/O)
  *
  * </center><br>
- *
  */
 
-#ifdef MODULE_PERIPH_CAN
-#include "can_esp.h"
+/**
+ * @name   USB device configuration
+ *
+ * ESP32x SoCs have:
+ * - a bidirectional control endpoint EP0 IN and EP0 OUT
+ * - six additional endpoints EP1 .. EP6 that can be configured as IN our OUT
+ * - a maximum of five IN endpoints concurrently active at any time (including EP0 IN)
+ * - all OUT endpoints share a single RX FIFO
+ * - each IN endpoint has a dedicated TX FIFO
+ *
+ * To avoid a lot of special case handling, the maximum number of IN an OUT
+ * endpoints including the control endpoint EP0 is 5.
+ *
+ * @{
+ */
+
+/**
+ * @brief   Enable the USB OTG FS peripheral
+ *
+ * At the moment, only FS is supported on ESP32x SoCs.
+ */
+#define DWC2_USB_OTG_FS_ENABLED         1
+
+/**
+ * @brief   Number of USB OTG FS IN endpoints including the control endpoint
+ */
+#define DWC2_USB_OTG_FS_NUM_EP          (5)
+
+/**
+ * @brief   Number of USB OTG HS OUT endpoints including the control endpoint
+ */
+#define DWC2_USB_OTG_HS_NUM_EP          (5)
+
+/**
+ * @brief   Size of the FIFO shared by all USB OTG FS OUT endpoints
+ */
+#ifndef DWC2_USB_OTG_FS_RX_FIFO_SIZE
+#define DWC2_USB_OTG_FS_RX_FIFO_SIZE    (128U)
 #endif
 
+/**
+ * @brief   Size of the FIFO shared by all USB OTG HS OUT endpoints
+ */
+#ifndef DWC2_USB_OTG_HS_RX_FIFO_SIZE
+#define DWC2_USB_OTG_HS_RX_FIFO_SIZE    (512U)
+#endif
+
+/**
+ * @brief   Total size of the FIFO
+ */
+#ifndef DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE
+#define DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE (1024U)
+#endif
+
+/**
+ * @brief   Buffers have to be word aligned for DMA
+ */
+#define USBDEV_CPU_DMA_ALIGNMENT        (4)
+/** @} */
+
+
 #ifdef __cplusplus
 }
 #endif

cpu/esp32/include/periph_cpu_esp32s3.h

@@ -215,10 +215,66 @@ extern "C" {
  *
  */
 
-#ifdef MODULE_PERIPH_CAN
-#include "can_esp.h"
+/**
+ * @name   USB device configuration
+ *
+ * ESP32x SoCs have:
+ * - a bidirectional control endpoint EP0 IN and EP0 OUT
+ * - six additional endpoints EP1 .. EP6 that can be configured as IN our OUT
+ * - a maximum of five IN endpoints concurrently active at any time (including EP0 IN)
+ * - all OUT endpoints share a single RX FIFO
+ * - each IN endpoint has a dedicated TX FIFO
+ *
+ * To avoid a lot of special case handling, the maximum number of IN an OUT
+ * endpoints including the control endpoint EP0 is 5.
+ *
+ * @{
+ */
+
+/**
+ * @brief   Enable the USB OTG FS peripheral
+ *
+ * At the moment, only FS is supported on ESP32x SoCs.
+ */
+#define DWC2_USB_OTG_FS_ENABLED         1
+
+/**
+ * @brief   Number of USB OTG FS IN endpoints including the control endpoint
+ */
+#define DWC2_USB_OTG_FS_NUM_EP          (5)
+
+/**
+ * @brief   Number of USB OTG HS OUT endpoints including the control endpoint
+ */
+#define DWC2_USB_OTG_HS_NUM_EP          (5)
+
+/**
+ * @brief   Size of the FIFO shared by all USB OTG FS OUT endpoints
+ */
+#ifndef DWC2_USB_OTG_FS_RX_FIFO_SIZE
+#define DWC2_USB_OTG_FS_RX_FIFO_SIZE    (128U)
 #endif
 
+/**
+ * @brief   Size of the FIFO shared by all USB OTG HS OUT endpoints
+ */
+#ifndef DWC2_USB_OTG_HS_RX_FIFO_SIZE
+#define DWC2_USB_OTG_HS_RX_FIFO_SIZE    (512U)
+#endif
+
+/**
+ * @brief   Total size of the FIFO
+ */
+#ifndef DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE
+#define DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE (1024U)
+#endif
+
+/**
+ * @brief   Buffers have to be word aligned for DMA
+ */
+#define USBDEV_CPU_DMA_ALIGNMENT        (4)
+/** @} */
+
 #ifdef __cplusplus
 }
 #endif

cpu/esp32/include/sdkconfig_esp32s2.h

@@ -105,9 +105,7 @@ extern "C" {
 /**
  * ESP32-S2 specific PHY configuration
  */
-#define CONFIG_USB_OTG_SUPPORTED 0
-#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256
-#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1
+#define CONFIG_USB_OTG_SUPPORTED                1
 
 /**
  * ESP32-S2 specific SPI RAM configuration

cpu/esp32/include/sdkconfig_esp32s3.h

@@ -110,9 +110,7 @@ extern "C" {
  * ESP32-S3 specific PHY configuration
  */
 #define CONFIG_ESP_PHY_ENABLE_USB               1
-#define CONFIG_USB_OTG_SUPPORTED 0
-#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256
-#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1
+#define CONFIG_USB_OTG_SUPPORTED                1
 
 /**
  * ESP32-S3 specific SPI RAM configuration

cpu/esp32/irq_arch.c

@@ -79,7 +79,10 @@ static const struct intr_handle_data_t _irq_data_table[] = {
 #if !defined(CPU_FAM_ESP32)
     { ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 },
 #endif
-    { ETS_INTERNAL_SW1_INTR_SOURCE, CPU_INUM_BLE, 2 }
+    { ETS_INTERNAL_SW1_INTR_SOURCE, CPU_INUM_BLE, 2 },
+#if defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
+    { ETS_USB_INTR_SOURCE, CPU_INUM_USB, 1 },
+#endif
 };
 
 #define IRQ_DATA_TABLE_SIZE        ARRAY_SIZE(_irq_data_table)

cpu/stm32/Makefile.dep

@@ -4,6 +4,9 @@
 USEMODULE += periph stm32_clk stm32_vectors
 
 ifneq (,$(filter periph_usbdev,$(FEATURES_USED)))
+  ifneq (wb,$(CPU_FAM))
+    USEMODULE += usbdev_synopsys_dwc2
+  endif
   USEMODULE += ztimer
   USEMODULE += ztimer_msec
 endif

cpu/stm32/include/periph/cpu_usbdev.h

@@ -39,46 +39,6 @@ extern "C" {
  */
 #define USBDEV_CPU_DMA_REQUIREMENTS    __attribute__((aligned(USBDEV_CPU_DMA_ALIGNMENT)))
 
-/**
- * @brief USB OTG peripheral type.
- *
- * High speed peripheral is assumed to have DMA support available.
- *
- * @warning Only one of each type is supported at the moment, it is not
- * supported to have two FS type or two HS type peripherals enabled on a
- * single MCU.
- */
-typedef enum {
-    STM32_USB_OTG_FS = 0,   /**< Full speed peripheral */
-    STM32_USB_OTG_HS = 1,   /**< High speed peripheral */
-} stm32_usb_otg_fshs_type_t;
-
-/**
- * @brief Type of USB OTG peripheral phy.
- *
- * The FS type only supports the built-in type, the HS phy can have either the
- * FS built-in phy enabled or the HS ULPI interface enabled.
- */
-typedef enum {
-    STM32_USB_OTG_PHY_BUILTIN,
-    STM32_USB_OTG_PHY_ULPI,
-} stm32_usb_otg_fshs_phy_t;
-
-/**
- * @brief stm32 USB OTG configuration
- */
-typedef struct {
-    uintptr_t periph;               /**< USB peripheral base address */
-    uint32_t rcc_mask;              /**< bit in clock enable register */
-    stm32_usb_otg_fshs_phy_t phy;   /**< Built-in or ULPI phy */
-    stm32_usb_otg_fshs_type_t type; /**< FS or HS type */
-    uint8_t irqn;                   /**< IRQ channel */
-    uint8_t ahb;                    /**< AHB bus */
-    gpio_t dm;                      /**< Data- gpio */
-    gpio_t dp;                      /**< Data+ gpio */
-    gpio_af_t af;                   /**< Alternative function */
-} stm32_usb_otg_fshs_config_t;
-
 /**
  * @brief stm32 USB device FS configuration
  */

cpu/stm32/include/usbdev_stm32.h

@@ -63,9 +63,9 @@ extern "C" {
  *        including the control endpoint
  */
 #ifdef STM32_USB_OTG_CID_1x
-#define STM32_USB_OTG_FS_NUM_EP (4) /**< OTG FS with 4 endpoints */
+#define DWC2_USB_OTG_FS_NUM_EP (4) /**< OTG FS with 4 endpoints */
 #elif defined(STM32_USB_OTG_CID_2x)
-#define STM32_USB_OTG_FS_NUM_EP (6) /**< OTG FS with 6 endpoints */
+#define DWC2_USB_OTG_FS_NUM_EP (6) /**< OTG FS with 6 endpoints */
 #endif
 
 /**
@@ -73,9 +73,9 @@ extern "C" {
  *        including the control endpoint
  */
 #ifdef STM32_USB_OTG_CID_1x
-#define STM32_USB_OTG_HS_NUM_EP (6) /**< OTG HS with 6 endpoints */
+#define DWC2_USB_OTG_HS_NUM_EP (6) /**< OTG HS with 6 endpoints */
 #elif defined(STM32_USB_OTG_CID_2x)
-#define STM32_USB_OTG_HS_NUM_EP (9) /**< OTG HS with 9 endpoints */
+#define DWC2_USB_OTG_HS_NUM_EP (9) /**< OTG HS with 9 endpoints */
 #endif
 
 /**
@@ -86,8 +86,8 @@ extern "C" {
  * @note The application might have to increase this when dealing with large
  *       isochronous transfers
  */
-#ifndef STM32_USB_OTG_FS_RX_FIFO_SIZE
-#define STM32_USB_OTG_FS_RX_FIFO_SIZE   (128U)
+#ifndef DWC2_USB_OTG_FS_RX_FIFO_SIZE
+#define DWC2_USB_OTG_FS_RX_FIFO_SIZE   (128U)
 #endif
 
 /**
@@ -95,8 +95,8 @@ extern "C" {
  *
  * Used as shared FIFO for reception of all OUT transfers from the host
  */
-#ifndef STM32_USB_OTG_HS_RX_FIFO_SIZE
-#define STM32_USB_OTG_HS_RX_FIFO_SIZE   (512U)
+#ifndef DWC2_USB_OTG_HS_RX_FIFO_SIZE
+#define DWC2_USB_OTG_HS_RX_FIFO_SIZE   (512U)
 #endif
 
 /**
@@ -112,26 +112,6 @@ extern "C" {
 #endif
 #endif
 
-/**
- * @brief stm32 USB OTG peripheral device out endpoint struct
- */
-typedef struct {
-    usbdev_ep_t ep;     /**< Inherited usbdev endpoint struct */
-    uint8_t *out_buf;   /**< Requested data output buffer */
-} stm32_usb_otg_fshs_out_ep_t;
-
-/**
- * @brief stm32 USB OTG peripheral device context
- */
-typedef struct {
-    usbdev_t usbdev;                            /**< Inherited usbdev struct */
-    const stm32_usb_otg_fshs_config_t *config;  /**< USB peripheral config   */
-    size_t fifo_pos;                            /**< FIFO space occupied */
-    usbdev_ep_t *in;                            /**< In endpoints */
-    stm32_usb_otg_fshs_out_ep_t *out;           /**< Out endpoints */
-    bool suspend;                               /**< Suspend status */
-} stm32_usb_otg_fshs_t;
-
 /**
  * @brief stm32 USB Device FS only peripheral device context
  */

cpu/stm32/periph/Kconfig

@@ -10,6 +10,7 @@ config MODULE_PERIPH
     default y
     select MODULE_ZTIMER if MODULE_PERIPH_USBDEV
     select MODULE_ZTIMER_MSEC if MODULE_PERIPH_USBDEV
+    select MODULE_USBDEV_SYNOPSYS_DWC2 if MODULE_PERIPH_USBDEV && !HAS_CPU_STM32WB
     help
         stm32 common peripheral code.
 

cpu/stm32/periph/Makefile

@@ -53,8 +53,6 @@ endif
 ifneq (,$(filter periph_usbdev,$(USEMODULE)))
   ifeq (wb,$(CPU_FAM))
     SRC += usbdev_fs.c
-  else
-    SRC += usbdev_otg.c
   endif
 endif
 

dist/tools/codespell/ignored_words.txt

@@ -137,3 +137,6 @@ clen
 
 # RO (read only) => to, row, rob, rod, roe, rot
 ro
+
+# Synopsys (vendor name) => Synopsis
+synopsys

drivers/Kconfig

@@ -57,6 +57,7 @@ rsource "periph_common/Kconfig"
 rsource "rtt_rtc/Kconfig"
 rsource "soft_spi/Kconfig"
 rsource "soft_uart/Kconfig"
+rsource "usbdev_synopsys_dwc2/Kconfig"
 endmenu # Peripherals drivers
 
 menu "Sensor Device Drivers"

drivers/Makefile.dep

@@ -195,6 +195,10 @@ ifneq (,$(filter tmp00%,$(USEMODULE)))
   USEMODULE += tmp00x
 endif
 
+ifneq (,$(filter usbdev_synopsys_dwc2,$(USEMODULE)))
+  FEATURES_REQUIRED += periph_usbdev
+endif
+
 ifneq (,$(filter vcnl40%0,$(USEMODULE)))
   USEMODULE += vcnl40x0
 endif

drivers/include/usbdev_synopsys_dwc2.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2019 Koen Zandberg
+ *               2022 Gunar Schorcht
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup drivers_periph_usbdev
+ * @{
+ *
+ * @file
+ * @brief   Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core
+ *
+ * @author  Koen Zandberg <koen@bergzand.net>
+ * @author  Gunar Schorcht <gunar@schorcht.net>
+ */
+
+#ifndef USBDEV_SYNOPSYS_DWC2_H
+#define USBDEV_SYNOPSYS_DWC2_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief USB OTG peripheral type.
+ *
+ * High speed peripheral is assumed to have DMA support available.
+ *
+ * @warning Only one of each type is supported at the moment, it is not
+ * supported to have two FS type or two HS type peripherals enabled on a
+ * single MCU.
+ */
+typedef enum {
+    DWC2_USB_OTG_FS = 0,   /**< Full speed peripheral */
+    DWC2_USB_OTG_HS = 1,   /**< High speed peripheral */
+} dwc2_usb_otg_fshs_type_t;
+
+#if defined(MCU_STM32)
+/**
+ * @brief Type of USB OTG peripheral phy.
+ *
+ * The FS type only supports the built-in type, the HS phy can have either the
+ * FS built-in phy enabled or the HS ULPI interface enabled.
+ */
+typedef enum {
+    DWC2_USB_OTG_PHY_BUILTIN,
+    DWC2_USB_OTG_PHY_ULPI,
+} dwc2_usb_otg_fshs_phy_t;
+#endif
+
+/**
+ * @brief stm32 USB OTG configuration
+ */
+typedef struct {
+    uintptr_t periph;               /**< USB peripheral base address */
+    dwc2_usb_otg_fshs_type_t type;  /**< FS or HS type */
+#if defined(MCU_STM32)
+    dwc2_usb_otg_fshs_phy_t phy;    /**< Built-in or ULPI phy */
+    uint32_t rcc_mask;              /**< bit in clock enable register */
+    uint8_t irqn;                   /**< IRQ channel */
+    uint8_t ahb;                    /**< AHB bus */
+    gpio_t dm;                      /**< Data- gpio */
+    gpio_t dp;                      /**< Data+ gpio */
+    gpio_af_t af;                   /**< Alternative function */
+#endif /* defined(MCU_STM32) */
+} dwc2_usb_otg_fshs_config_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USBDEV_SYNOPSYS_DWC2_H */
+/** @} */

drivers/usbdev_synopsys_dwc2/Kconfig

@@ -0,0 +1,14 @@
+# Copyright (c) 2021 HAW Hamburg
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config MODULE_USBDEV_SYNOPSYS_DWC2
+    bool
+    depends on TEST_KCONFIG
+    depends on HAS_PERIPH_USBDEV
+    select MODULE_ZTIMER_MSEC
+    help
+         USBDEV low-level driver for MCUs with Synopsys DWC2 USB OTG FS/HS IP core"

drivers/usbdev_synopsys_dwc2/Makefile

@@ -0,0 +1 @@
+include $(RIOTBASE)/Makefile.base