diff --git a/boards/common/esp32s2/include/periph_conf_common.h b/boards/common/esp32s2/include/periph_conf_common.h index eb004b8f0a..47c663e9c3 100644 --- a/boards/common/esp32s2/include/periph_conf_common.h +++ b/boards/common/esp32s2/include/periph_conf_common.h @@ -337,6 +337,31 @@ static const uart_conf_t uart_config[] = { #define UART_NUMOF ARRAY_SIZE(uart_config) /** @} */ +/** + * @name USB device configuration + * + * @{ + */ + +#include "usbdev_esp32.h" + +/** + * @brief Static array with USB OTG FS configuration + */ +static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = { + { + .periph = USB_OTG_FS_PERIPH_BASE, + .type = DWC2_USB_OTG_FS, + } +}; + +/** + * @brief Number of USB OTG FS interfaces + */ +#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config) + +/** @} */ + #ifdef __cplusplus } /* end extern "C" */ #endif diff --git a/boards/common/esp32s3/include/periph_conf_common.h b/boards/common/esp32s3/include/periph_conf_common.h index 13233b93c8..0d6002f211 100644 --- a/boards/common/esp32s3/include/periph_conf_common.h +++ b/boards/common/esp32s3/include/periph_conf_common.h @@ -337,6 +337,31 @@ static const uart_conf_t uart_config[] = { #define UART_NUMOF ARRAY_SIZE(uart_config) /** @} */ +/** + * @name USB device configuration + * + * @{ + */ + +#include "usbdev_esp32.h" + +/** + * @brief Static array with USB OTG FS configuration + */ +static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = { + { + .periph = USB_OTG_FS_PERIPH_BASE, + .type = DWC2_USB_OTG_FS, + } +}; + +/** + * @brief Number of USB OTG FS interfaces + */ +#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config) + +/** @} */ + #ifdef __cplusplus } /* end extern "C" */ #endif diff --git a/boards/common/stm32/include/cfg_usb_otg_fs.h b/boards/common/stm32/include/cfg_usb_otg_fs.h index eba39f8f2c..fd3b888000 100644 --- a/boards/common/stm32/include/cfg_usb_otg_fs.h +++ b/boards/common/stm32/include/cfg_usb_otg_fs.h @@ -20,6 +20,7 @@ #define CFG_USB_OTG_FS_H #include "periph_cpu.h" +#include "usbdev_synopsys_dwc2.h" #ifdef __cplusplus extern "C" { @@ -28,18 +29,17 @@ extern "C" { /** * @brief Enable the full speed USB OTG peripheral */ -#define STM32_USB_OTG_FS_ENABLED +#define DWC2_USB_OTG_FS_ENABLED /** - * @name common USB OTG FS configuration - * @{ + * @brief Common USB OTG FS configuration */ -static const stm32_usb_otg_fshs_config_t stm32_usb_otg_fshs_config[] = { +static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = { { .periph = USB_OTG_FS_PERIPH_BASE, + .type = DWC2_USB_OTG_FS, + .phy = DWC2_USB_OTG_PHY_BUILTIN, .rcc_mask = RCC_AHB2ENR_OTGFSEN, - .phy = STM32_USB_OTG_PHY_BUILTIN, - .type = STM32_USB_OTG_FS, .irqn = OTG_FS_IRQn, .ahb = AHB2, .dm = GPIO_PIN(PORT_A, 11), @@ -47,12 +47,11 @@ static const stm32_usb_otg_fshs_config_t stm32_usb_otg_fshs_config[] = { .af = GPIO_AF10, } }; -/** @} */ /** * @brief Number of available USB OTG peripherals */ -#define USBDEV_NUMOF ARRAY_SIZE(stm32_usb_otg_fshs_config) +#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config) #ifdef __cplusplus } diff --git a/boards/common/stm32/include/cfg_usb_otg_hs_fs.h b/boards/common/stm32/include/cfg_usb_otg_hs_fs.h index a95f560c2d..c861f5e466 100644 --- a/boards/common/stm32/include/cfg_usb_otg_hs_fs.h +++ b/boards/common/stm32/include/cfg_usb_otg_hs_fs.h @@ -20,6 +20,7 @@ #define CFG_USB_OTG_HS_FS_H #include "periph_cpu.h" +#include "usbdev_synopsys_dwc2.h" #ifdef __cplusplus extern "C" { @@ -28,18 +29,17 @@ extern "C" { /** * @brief Enable the full speed USB OTG peripheral */ -#define STM32_USB_OTG_HS_ENABLED +#define DWC2_USB_OTG_HS_ENABLED /** - * @name common USB OTG FS configuration - * @{ + * @brief Common USB OTG FS configuration */ -static const stm32_usb_otg_fshs_config_t stm32_usb_otg_fshs_config[] = { +static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = { { .periph = USB_OTG_HS_PERIPH_BASE, + .type = DWC2_USB_OTG_HS, + .phy = DWC2_USB_OTG_PHY_BUILTIN, .rcc_mask = RCC_AHB1ENR_OTGHSEN, - .phy = STM32_USB_OTG_PHY_BUILTIN, - .type = STM32_USB_OTG_HS, .irqn = OTG_HS_IRQn, .ahb = AHB1, .dm = GPIO_PIN(PORT_B, 14), @@ -47,12 +47,11 @@ static const stm32_usb_otg_fshs_config_t stm32_usb_otg_fshs_config[] = { .af = GPIO_AF12, } }; -/** @} */ /** * @brief Number of available USB OTG peripherals */ -#define USBDEV_NUMOF ARRAY_SIZE(stm32_usb_otg_fshs_config) +#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config) #ifdef __cplusplus } diff --git a/boards/esp32s2-devkit/Kconfig b/boards/esp32s2-devkit/Kconfig index 9b22afca5e..ec8398c4a4 100644 --- a/boards/esp32s2-devkit/Kconfig +++ b/boards/esp32s2-devkit/Kconfig @@ -30,10 +30,14 @@ config BOARD_ESP32S2_DEVKIT select HAS_PERIPH_I2C select HAS_PERIPH_PWM select HAS_PERIPH_SPI + select HAS_PERIPH_USBDEV if BOARD_VERSION_ESP32S2_DEVKITC_1 + select HAS_PERIPH_USBDEV if BOARD_VERSION_ESP32S2_DEVKITC_1U + select HAS_PERIPH_USBDEV if BOARD_VERSION_ESP32S2_DEVKITC_1R + select HAS_PERIPH_USBDEV if BOARD_VERSION_ESP32S2_DEVKITC_1RU choice bool "ESP32-S2-DevKit board version" - default BOARD_VERSION_ESP32S2_DEVKITM_1 + default BOARD_VERSION_ESP32S2_DEVKITC_1 config BOARD_VERSION_ESP32S2_DEVKITM_1 bool "ESP32-S2-DevKitM-1" diff --git a/boards/esp32s2-devkit/Makefile.features b/boards/esp32s2-devkit/Makefile.features index be5a9fd5f5..7968cc24cc 100644 --- a/boards/esp32s2-devkit/Makefile.features +++ b/boards/esp32s2-devkit/Makefile.features @@ -1,17 +1,17 @@ # default board version if not defined -BOARD_VERSION ?= esp32s2-devkitm-1 +BOARD_VERSION ?= esp32s2-devkitc-1 ifeq (esp32s2-devkitm-1,$(BOARD_VERSION)) CPU_MODEL = esp32s2_mini_1x_n4 else ifeq (esp32s2-devkitm-1u,$(BOARD_VERSION)) CPU_MODEL = esp32s2_mini_1x_n4 else ifeq (esp32s2-devkitm-1r,$(BOARD_VERSION)) - CPU_MODEL = esp32s2_mini-1x_n4r2 + CPU_MODEL = esp32s2_mini_1x_n4r2 else ifeq (esp32s2-devkitm-1ru,$(BOARD_VERSION)) - CPU_MODEL = esp32s2_mini-1x_n4r2 -else ifeq (esp32s2-devkitc_1,$(BOARD_VERSION)) + CPU_MODEL = esp32s2_mini_1x_n4r2 +else ifeq (esp32s2-devkitc-1,$(BOARD_VERSION)) CPU_MODEL = esp32s2_solo_n4 -else ifeq (esp32s2-devkitc_1u,$(BOARD_VERSION)) +else ifeq (esp32s2-devkitc-1u,$(BOARD_VERSION)) CPU_MODEL = esp32s2_solo_n4 else ifeq (esp32s2-devkitc-1r,$(BOARD_VERSION)) CPU_MODEL = esp32s2_solo_n4r2 @@ -40,3 +40,7 @@ FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_spi FEATURES_PROVIDED += arduino + +ifneq (,$(filter esp32s2-devkitc-%,$(BOARD_VERSION))) + FEATURES_PROVIDED += periph_usbdev +endif diff --git a/boards/esp32s3-devkit/Kconfig b/boards/esp32s3-devkit/Kconfig index ca4e601b83..141af216c8 100644 --- a/boards/esp32s3-devkit/Kconfig +++ b/boards/esp32s3-devkit/Kconfig @@ -43,6 +43,7 @@ config BOARD_ESP32S3_DEVKIT select HAS_PERIPH_I2C select HAS_PERIPH_PWM select HAS_PERIPH_SPI + select HAS_PERIPH_USBDEV choice bool "ESP32-S3-DevKit board version" diff --git a/boards/esp32s3-devkit/Makefile.features b/boards/esp32s3-devkit/Makefile.features index c128172e06..29ce79cba2 100644 --- a/boards/esp32s3-devkit/Makefile.features +++ b/boards/esp32s3-devkit/Makefile.features @@ -38,3 +38,4 @@ FEATURES_PROVIDED += periph_spi FEATURES_PROVIDED += esp_jtag FEATURES_PROVIDED += arduino +FEATURES_PROVIDED += periph_usbdev diff --git a/cpu/esp32/Kconfig.esp32s2 b/cpu/esp32/Kconfig.esp32s2 index 6478c56238..275ad3f7f1 100644 --- a/cpu/esp32/Kconfig.esp32s2 +++ b/cpu/esp32/Kconfig.esp32s2 @@ -25,6 +25,7 @@ config CPU_FAM_ESP32S2 select MODULE_PS if MODULE_SHELL select MODULE_PTHREAD if MODULE_CPP select MODULE_RTT_RTC if HAS_PERIPH_RTT && MODULE_PERIPH_RTC + select MODULE_USBDEV_SYNOPSYS_DWC2 if HAS_PERIPH_USBDEV && MODULE_PERIPH_USBDEV imply MODULE_NEWLIB_NANO config CPU_FAM diff --git a/cpu/esp32/Kconfig.esp32s3 b/cpu/esp32/Kconfig.esp32s3 index ddbd1f2408..83d7c47e57 100644 --- a/cpu/esp32/Kconfig.esp32s3 +++ b/cpu/esp32/Kconfig.esp32s3 @@ -31,6 +31,7 @@ config CPU_FAM_ESP32S3 select MODULE_PS if MODULE_SHELL select MODULE_PTHREAD if MODULE_CPP select MODULE_RTT_RTC if HAS_PERIPH_RTT && MODULE_PERIPH_RTC + select MODULE_USBDEV_SYNOPSYS_DWC2 if HAS_PERIPH_USBDEV && MODULE_PERIPH_USBDEV imply MODULE_NEWLIB_NANO config CPU_FAM diff --git a/cpu/esp32/Makefile.dep b/cpu/esp32/Makefile.dep index f3da321258..5ada3f39ab 100644 --- a/cpu/esp32/Makefile.dep +++ b/cpu/esp32/Makefile.dep @@ -157,6 +157,12 @@ ifneq (,$(filter periph_rtt,$(USEMODULE))) USEMODULE += periph_rtt_hw_rtc endif +ifneq (,$(filter periph_usbdev,$(USEMODULE))) + USEMODULE += esp_idf_usb + USEMODULE += usbdev_synopsys_dwc2 + USEMODULE += ztimer_msec +endif + ifneq (,$(filter shell,$(USEMODULE))) USEMODULE += ps endif diff --git a/cpu/esp32/Makefile.include b/cpu/esp32/Makefile.include index 3ad8e4d909..d1123dfd75 100644 --- a/cpu/esp32/Makefile.include +++ b/cpu/esp32/Makefile.include @@ -50,6 +50,7 @@ PSEUDOMODULES += esp_wifi_enterprise INCLUDES += -I$(RIOTCPU)/$(CPU)/esp-idf/include INCLUDES += -I$(RIOTCPU)/$(CPU)/esp-idf/include/log +INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/include INCLUDES += -I$(ESP32_SDK_DIR)/components INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/include @@ -98,6 +99,10 @@ ifneq (,$(filter esp_idf_spi_flash,$(USEMODULE))) INCLUDES += -I$(ESP32_SDK_DIR)/components/spi_flash/include endif +ifneq (,$(filter esp_idf_usb,$(USEMODULE))) + INCLUDES += -I$(ESP32_SDK_DIR)/components/usb/include +endif + ifneq (,$(filter esp_wifi_any,$(USEMODULE))) INCLUDES += -I$(ESP32_SDK_DIR)/components/bootloader_support/include INCLUDES += -I$(ESP32_SDK_DIR)/components/esp_eth/include diff --git a/cpu/esp32/esp-idf/Kconfig b/cpu/esp32/esp-idf/Kconfig index f2622529c1..7702960912 100644 --- a/cpu/esp32/esp-idf/Kconfig +++ b/cpu/esp32/esp-idf/Kconfig @@ -28,5 +28,6 @@ rsource "heap/Kconfig" rsource "nvs_flash/Kconfig" rsource "spi_flash/Kconfig" rsource "spi_ram/Kconfig" +rsource "usb/Kconfig" rsource "wifi/Kconfig" rsource "wpa_supplicant/Kconfig" diff --git a/cpu/esp32/esp-idf/Makefile b/cpu/esp32/esp-idf/Makefile index fe07dade5f..21ccf13245 100644 --- a/cpu/esp32/esp-idf/Makefile +++ b/cpu/esp32/esp-idf/Makefile @@ -48,6 +48,10 @@ ifneq (,$(filter esp_idf_spi_ram,$(USEMODULE))) DIRS += spi_ram endif +ifneq (,$(filter esp_idf_usb,$(USEMODULE))) + DIRS += usb +endif + ifneq (,$(filter esp_idf_wifi,$(USEMODULE))) DIRS += wifi endif diff --git a/cpu/esp32/esp-idf/usb/Kconfig b/cpu/esp32/esp-idf/usb/Kconfig new file mode 100644 index 0000000000..db41973f8f --- /dev/null +++ b/cpu/esp32/esp-idf/usb/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2022 Gunar Schorcht +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +config MODULE_ESP_IDF_USB + bool + depends on TEST_KCONFIG + depends on MODULE_ESP_IDF + default y if MODULE_PERIPH_USBDEV + help + ESP-IDF code for USB. diff --git a/cpu/esp32/esp-idf/usb/Makefile b/cpu/esp32/esp-idf/usb/Makefile new file mode 100644 index 0000000000..3261f5fc13 --- /dev/null +++ b/cpu/esp32/esp-idf/usb/Makefile @@ -0,0 +1,17 @@ +MODULE = esp_idf_usb + +# source files to be compiled for this module +ESP32_SDK_SRC = \ + components/hal/usb_hal.c \ + components/hal/usb_phy_hal.c \ + components/soc/$(CPU_FAM)/usb_periph.c \ + components/soc/$(CPU_FAM)/usb_phy_periph.c \ + components/usb/usb_phy.c \ + # + +include $(RIOTBASE)/Makefile.base + +ESP32_SDK_BIN = $(BINDIR)/$(MODULE) + +include ../esp_idf.mk +include ../esp_idf_cflags.mk diff --git a/cpu/esp32/include/irq_arch.h b/cpu/esp32/include/irq_arch.h index d1fed2658b..faccdf1916 100644 --- a/cpu/esp32/include/irq_arch.h +++ b/cpu/esp32/include/irq_arch.h @@ -39,6 +39,7 @@ extern "C" { #define CPU_INUM_GPIO 2 /**< Level interrupt with low priority 1 */ #define CPU_INUM_CAN 3 /**< Level interrupt with low priority 1 */ #define CPU_INUM_UART 4 /**< Level interrupt with low priority 1 */ +#define CPU_INUM_USB 8 /**< Level interrupt with low priority 1 */ #define CPU_INUM_RTT 9 /**< Level interrupt with low priority 1 */ #define CPU_INUM_I2C 12 /**< Level interrupt with low priority 1 */ #define CPU_INUM_WDT 13 /**< Level interrupt with low priority 1 */ diff --git a/cpu/esp32/include/periph_cpu.h b/cpu/esp32/include/periph_cpu.h index a3d419bbb4..10a5761c5a 100644 --- a/cpu/esp32/include/periph_cpu.h +++ b/cpu/esp32/include/periph_cpu.h @@ -811,7 +811,21 @@ typedef struct { /** * @brief Maximum number of UART interfaces */ -#define UART_NUMOF_MAX (SOC_UART_NUM) +#define UART_NUMOF_MAX (SOC_UART_NUM) +/** @} */ + +/** + * @name USB device configuration + * @{ + * + * ESP32x SoCs integrate depending on the specific ESP32x SoC variant (family) an USB OTG FS controller based on the Synopsys DWC2 IP core. + */ +#include "usbdev_synopsys_dwc2.h" + +/** + * @brief Maximum number of USB OTG FS interfaces + */ +#define USBDEV_NUMOF_MAX (SOC_USB_PERIPH_NUM) /** @} */ #ifdef __cplusplus diff --git a/cpu/esp32/include/periph_cpu_esp32c3.h b/cpu/esp32/include/periph_cpu_esp32c3.h index f4bab20a77..e2b243280a 100644 --- a/cpu/esp32/include/periph_cpu_esp32c3.h +++ b/cpu/esp32/include/periph_cpu_esp32c3.h @@ -167,10 +167,6 @@ extern "C" { * */ -#ifdef MODULE_PERIPH_CAN -#include "can_esp.h" -#endif - #ifdef __cplusplus } #endif diff --git a/cpu/esp32/include/periph_cpu_esp32s2.h b/cpu/esp32/include/periph_cpu_esp32s2.h index 74ffd6ed00..5f9f6b572e 100644 --- a/cpu/esp32/include/periph_cpu_esp32s2.h +++ b/cpu/esp32/include/periph_cpu_esp32s2.h @@ -212,13 +212,69 @@ extern "C" { * UART_DEV(2) | RxD | - |`UART2_RXD` | optional, can be overridden (no direct I/O) * *
- * */ -#ifdef MODULE_PERIPH_CAN -#include "can_esp.h" +/** + * @name USB device configuration + * + * ESP32x SoCs have: + * - a bidirectional control endpoint EP0 IN and EP0 OUT + * - six additional endpoints EP1 .. EP6 that can be configured as IN our OUT + * - a maximum of five IN endpoints concurrently active at any time (including EP0 IN) + * - all OUT endpoints share a single RX FIFO + * - each IN endpoint has a dedicated TX FIFO + * + * To avoid a lot of special case handling, the maximum number of IN an OUT + * endpoints including the control endpoint EP0 is 5. + * + * @{ + */ + +/** + * @brief Enable the USB OTG FS peripheral + * + * At the moment, only FS is supported on ESP32x SoCs. + */ +#define DWC2_USB_OTG_FS_ENABLED 1 + +/** + * @brief Number of USB OTG FS IN endpoints including the control endpoint + */ +#define DWC2_USB_OTG_FS_NUM_EP (5) + +/** + * @brief Number of USB OTG HS OUT endpoints including the control endpoint + */ +#define DWC2_USB_OTG_HS_NUM_EP (5) + +/** + * @brief Size of the FIFO shared by all USB OTG FS OUT endpoints + */ +#ifndef DWC2_USB_OTG_FS_RX_FIFO_SIZE +#define DWC2_USB_OTG_FS_RX_FIFO_SIZE (128U) #endif +/** + * @brief Size of the FIFO shared by all USB OTG HS OUT endpoints + */ +#ifndef DWC2_USB_OTG_HS_RX_FIFO_SIZE +#define DWC2_USB_OTG_HS_RX_FIFO_SIZE (512U) +#endif + +/** + * @brief Total size of the FIFO + */ +#ifndef DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE +#define DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE (1024U) +#endif + +/** + * @brief Buffers have to be word aligned for DMA + */ +#define USBDEV_CPU_DMA_ALIGNMENT (4) +/** @} */ + + #ifdef __cplusplus } #endif diff --git a/cpu/esp32/include/periph_cpu_esp32s3.h b/cpu/esp32/include/periph_cpu_esp32s3.h index 2856d39cfe..90e5c5b5c0 100644 --- a/cpu/esp32/include/periph_cpu_esp32s3.h +++ b/cpu/esp32/include/periph_cpu_esp32s3.h @@ -215,10 +215,66 @@ extern "C" { * */ -#ifdef MODULE_PERIPH_CAN -#include "can_esp.h" +/** + * @name USB device configuration + * + * ESP32x SoCs have: + * - a bidirectional control endpoint EP0 IN and EP0 OUT + * - six additional endpoints EP1 .. EP6 that can be configured as IN our OUT + * - a maximum of five IN endpoints concurrently active at any time (including EP0 IN) + * - all OUT endpoints share a single RX FIFO + * - each IN endpoint has a dedicated TX FIFO + * + * To avoid a lot of special case handling, the maximum number of IN an OUT + * endpoints including the control endpoint EP0 is 5. + * + * @{ + */ + +/** + * @brief Enable the USB OTG FS peripheral + * + * At the moment, only FS is supported on ESP32x SoCs. + */ +#define DWC2_USB_OTG_FS_ENABLED 1 + +/** + * @brief Number of USB OTG FS IN endpoints including the control endpoint + */ +#define DWC2_USB_OTG_FS_NUM_EP (5) + +/** + * @brief Number of USB OTG HS OUT endpoints including the control endpoint + */ +#define DWC2_USB_OTG_HS_NUM_EP (5) + +/** + * @brief Size of the FIFO shared by all USB OTG FS OUT endpoints + */ +#ifndef DWC2_USB_OTG_FS_RX_FIFO_SIZE +#define DWC2_USB_OTG_FS_RX_FIFO_SIZE (128U) #endif +/** + * @brief Size of the FIFO shared by all USB OTG HS OUT endpoints + */ +#ifndef DWC2_USB_OTG_HS_RX_FIFO_SIZE +#define DWC2_USB_OTG_HS_RX_FIFO_SIZE (512U) +#endif + +/** + * @brief Total size of the FIFO + */ +#ifndef DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE +#define DWC2_USB_OTG_FS_TOTAL_FIFO_SIZE (1024U) +#endif + +/** + * @brief Buffers have to be word aligned for DMA + */ +#define USBDEV_CPU_DMA_ALIGNMENT (4) +/** @} */ + #ifdef __cplusplus } #endif diff --git a/cpu/esp32/include/sdkconfig_esp32s2.h b/cpu/esp32/include/sdkconfig_esp32s2.h index 5969ce2e37..d80d3c2c1e 100644 --- a/cpu/esp32/include/sdkconfig_esp32s2.h +++ b/cpu/esp32/include/sdkconfig_esp32s2.h @@ -105,9 +105,7 @@ extern "C" { /** * ESP32-S2 specific PHY configuration */ -#define CONFIG_USB_OTG_SUPPORTED 0 -#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256 -#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1 +#define CONFIG_USB_OTG_SUPPORTED 1 /** * ESP32-S2 specific SPI RAM configuration diff --git a/cpu/esp32/include/sdkconfig_esp32s3.h b/cpu/esp32/include/sdkconfig_esp32s3.h index 0c10f474a9..511061867e 100644 --- a/cpu/esp32/include/sdkconfig_esp32s3.h +++ b/cpu/esp32/include/sdkconfig_esp32s3.h @@ -110,9 +110,7 @@ extern "C" { * ESP32-S3 specific PHY configuration */ #define CONFIG_ESP_PHY_ENABLE_USB 1 -#define CONFIG_USB_OTG_SUPPORTED 0 -#define CONFIG_USB_HOST_CONTROL_TRANSFER_MAX_SIZE 256 -#define CONFIG_USB_HOST_HW_BUFFER_BIAS_BALANCED 1 +#define CONFIG_USB_OTG_SUPPORTED 1 /** * ESP32-S3 specific SPI RAM configuration diff --git a/cpu/esp32/irq_arch.c b/cpu/esp32/irq_arch.c index a33772b0d5..f43e304824 100644 --- a/cpu/esp32/irq_arch.c +++ b/cpu/esp32/irq_arch.c @@ -79,7 +79,10 @@ static const struct intr_handle_data_t _irq_data_table[] = { #if !defined(CPU_FAM_ESP32) { ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, CPU_INUM_SYSTIMER, 2 }, #endif - { ETS_INTERNAL_SW1_INTR_SOURCE, CPU_INUM_BLE, 2 } + { ETS_INTERNAL_SW1_INTR_SOURCE, CPU_INUM_BLE, 2 }, +#if defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3) + { ETS_USB_INTR_SOURCE, CPU_INUM_USB, 1 }, +#endif }; #define IRQ_DATA_TABLE_SIZE ARRAY_SIZE(_irq_data_table) diff --git a/cpu/esp32/vendor/include/usbdev_esp32.h b/cpu/esp32/vendor/include/usbdev_esp32.h new file mode 100644 index 0000000000..7bd4e39c13 --- /dev/null +++ b/cpu/esp32/vendor/include/usbdev_esp32.h @@ -0,0 +1,1535 @@ +/** + * @author MCD Application Team + * @brief OTG_FS definitions for Synopsys DWC2 IP core of ESP32x SoCs + * + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ + +#ifndef USBDEV_ESP32_H +#define USBDEV_ESP32_H + +#ifndef DOXYGEN + +#define USB_OTG_FS_PERIPH_BASE 0x60080000UL +#define USB_OTG_GLOBAL_BASE 0x0000UL +#define USB_OTG_DEVICE_BASE 0x0800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL +#define USB_OTG_EP_REG_SIZE 0x0020UL +#define USB_OTG_HOST_BASE 0x0400UL +#define USB_OTG_HOST_PORT_BASE 0x0440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL +#define USB_OTG_PCGCCTL_BASE 0x0E00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +/* define macros that are used for volatile keyword in STM32 header files */ +#define __I volatile +#define __O volatile +#define __IO volatile + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[3]; /*!< Reserved 030h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + uint32_t Reserved7; /*!< Reserved 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +/******************************************************************************/ +/* */ +/* USB_OTG */ +/* */ +/******************************************************************************/ +/******************** Bit definition for USB_OTG_GOTGCTL register ********************/ +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ +#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) +#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ +#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) +#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ +#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ +#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U) +#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) +#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ +#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U) +#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) +#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ + +/******************** Bit definition for USB_OTG_HCFG register ********************/ +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ + +/******************** Bit definition for USB_OTG_DCFG register ********************/ +#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for USB_OTG_PCGCR register ********************/ +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ + +/******************** Bit definition for USB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ +#define USB_OTG_GOTGINT_IDCHNG_Pos (20U) +#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */ + +/******************** Bit definition for USB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ + +/******************** Bit definition for USB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ + +/******************** Bit definition for USB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ + +/******************** Bit definition for USB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ + +/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ + +/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ + +/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for USB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ + +/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKM_Pos (13U) +#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETM_Pos (14U) +#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_LPMINT_Pos (27U) +#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ +#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */ +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition for USB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDEM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_LPMINTM_Pos (27U) +#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ +#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition for USB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ + +/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for OTG register ********************/ + +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ + +/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ + +/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ + +/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ + +/******************** Bit definition for USB_OTG_GCCFG register ********************/ +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ +#define USB_OTG_GCCFG_VBDEN_Pos (21U) +#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */ + +/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ + +/******************** Bit definition for USB_OTG_CID register ********************/ +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ + +/******************** Bit definition for USB_OTG_GLPMCFG register ********************/ +#define USB_OTG_GLPMCFG_LPMEN_Pos (0U) +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */ + +/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ + +/******************** Bit definition for USB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ +#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ + +#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ + +#define USB_OTG_HCCHAR_MC_Pos (20U) +#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ + +#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ + +/******************** Bit definition for USB_OTG_HCSPLT register ********************/ + +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ + +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ + +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ + +/******************** Bit definition for USB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ + +/******************** Bit definition for USB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_AHBERR_Pos (2U) +#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ + +/******************** Bit definition for USB_OTG_HCINTMSK register ********************/ +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ + +/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ + +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ + +/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ +#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*! to, row, rob, rod, roe, rot ro + +# Synopsys (vendor name) => Synopsis +synopsys diff --git a/drivers/Kconfig b/drivers/Kconfig index fafebeab74..6206ae378b 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -57,6 +57,7 @@ rsource "periph_common/Kconfig" rsource "rtt_rtc/Kconfig" rsource "soft_spi/Kconfig" rsource "soft_uart/Kconfig" +rsource "usbdev_synopsys_dwc2/Kconfig" endmenu # Peripherals drivers menu "Sensor Device Drivers" diff --git a/drivers/Makefile.dep b/drivers/Makefile.dep index 5573f73588..09f99693d3 100644 --- a/drivers/Makefile.dep +++ b/drivers/Makefile.dep @@ -195,6 +195,10 @@ ifneq (,$(filter tmp00%,$(USEMODULE))) USEMODULE += tmp00x endif +ifneq (,$(filter usbdev_synopsys_dwc2,$(USEMODULE))) + FEATURES_REQUIRED += periph_usbdev +endif + ifneq (,$(filter vcnl40%0,$(USEMODULE))) USEMODULE += vcnl40x0 endif diff --git a/drivers/include/usbdev_synopsys_dwc2.h b/drivers/include/usbdev_synopsys_dwc2.h new file mode 100644 index 0000000000..9f2174c778 --- /dev/null +++ b/drivers/include/usbdev_synopsys_dwc2.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2019 Koen Zandberg + * 2022 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_periph_usbdev + * @{ + * + * @file + * @brief Low level USB FS/HS driver definitions for MCUs with Synopsys DWC2 IP core + * + * @author Koen Zandberg + * @author Gunar Schorcht + */ + +#ifndef USBDEV_SYNOPSYS_DWC2_H +#define USBDEV_SYNOPSYS_DWC2_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief USB OTG peripheral type. + * + * High speed peripheral is assumed to have DMA support available. + * + * @warning Only one of each type is supported at the moment, it is not + * supported to have two FS type or two HS type peripherals enabled on a + * single MCU. + */ +typedef enum { + DWC2_USB_OTG_FS = 0, /**< Full speed peripheral */ + DWC2_USB_OTG_HS = 1, /**< High speed peripheral */ +} dwc2_usb_otg_fshs_type_t; + +#if defined(MCU_STM32) +/** + * @brief Type of USB OTG peripheral phy. + * + * The FS type only supports the built-in type, the HS phy can have either the + * FS built-in phy enabled or the HS ULPI interface enabled. + */ +typedef enum { + DWC2_USB_OTG_PHY_BUILTIN, + DWC2_USB_OTG_PHY_ULPI, +} dwc2_usb_otg_fshs_phy_t; +#endif + +/** + * @brief stm32 USB OTG configuration + */ +typedef struct { + uintptr_t periph; /**< USB peripheral base address */ + dwc2_usb_otg_fshs_type_t type; /**< FS or HS type */ +#if defined(MCU_STM32) + dwc2_usb_otg_fshs_phy_t phy; /**< Built-in or ULPI phy */ + uint32_t rcc_mask; /**< bit in clock enable register */ + uint8_t irqn; /**< IRQ channel */ + uint8_t ahb; /**< AHB bus */ + gpio_t dm; /**< Data- gpio */ + gpio_t dp; /**< Data+ gpio */ + gpio_af_t af; /**< Alternative function */ +#endif /* defined(MCU_STM32) */ +} dwc2_usb_otg_fshs_config_t; + +#ifdef __cplusplus +} +#endif + +#endif /* USBDEV_SYNOPSYS_DWC2_H */ +/** @} */ diff --git a/drivers/usbdev_synopsys_dwc2/Kconfig b/drivers/usbdev_synopsys_dwc2/Kconfig new file mode 100644 index 0000000000..3dc40d1287 --- /dev/null +++ b/drivers/usbdev_synopsys_dwc2/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2021 HAW Hamburg +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +config MODULE_USBDEV_SYNOPSYS_DWC2 + bool + depends on TEST_KCONFIG + depends on HAS_PERIPH_USBDEV + select MODULE_ZTIMER_MSEC + help + USBDEV low-level driver for MCUs with Synopsys DWC2 USB OTG FS/HS IP core" diff --git a/drivers/usbdev_synopsys_dwc2/Makefile b/drivers/usbdev_synopsys_dwc2/Makefile new file mode 100644 index 0000000000..48422e909a --- /dev/null +++ b/drivers/usbdev_synopsys_dwc2/Makefile @@ -0,0 +1 @@ +include $(RIOTBASE)/Makefile.base diff --git a/cpu/stm32/periph/usbdev_otg.c b/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c similarity index 70% rename from cpu/stm32/periph/usbdev_otg.c rename to drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c index 89ba257079..ece0dfafd7 100644 --- a/cpu/stm32/periph/usbdev_otg.c +++ b/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2019 Koen Zandberg + * 2022 Gunar Schorcht * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level @@ -7,10 +8,10 @@ */ /** - * @ingroup cpu_stm32_usbdev + * @ingroup drivers_periph_usbdev * @{ * @file - * @brief Low level USB interface functions for the stm32 FS/HS devices + * @brief Low level USB FS/HS driver for MCUs with Synopsys DWC2 IP core * * @author Koen Zandberg * @} @@ -18,6 +19,14 @@ #define USB_H_USER_IS_RIOT_INTERNAL +#ifdef MCU_ESP32 + +#if !defined(CPU_FAM_ESP32S2) && !defined(CPU_FAM_ESP32S3) +#error "ESP32x SoC family not supported" +#endif /* !defined(CPU_FAM_ESP32S2) && !defined(CPU_FAM_ESP32S3) */ + +#endif + #include #include #include @@ -25,14 +34,22 @@ #include "architecture.h" #include "bitarithm.h" -#include "ztimer.h" #include "cpu.h" #include "cpu_conf.h" +#include "log.h" #include "periph/pm.h" #include "periph/gpio.h" #include "periph/usbdev.h" #include "pm_layered.h" +#include "ztimer.h" + +#if defined(MCU_STM32) #include "usbdev_stm32.h" +#elif defined(MCU_ESP32) +#include "usbdev_esp32.h" +#else +#error "MCU not supported" +#endif /** * Be careful with enabling debug here. As with all timing critical systems it @@ -42,17 +59,26 @@ #define ENABLE_DEBUG 0 #include "debug.h" -#if defined(STM32_USB_OTG_FS_ENABLED) && defined(STM32_USB_OTG_HS_ENABLED) -#define _TOTAL_NUM_ENDPOINTS (STM32_USB_OTG_FS_NUM_EP + \ - STM32_USB_OTG_HS_NUM_EP) -#elif defined(STM32_USB_OTG_FS_ENABLED) -#define _TOTAL_NUM_ENDPOINTS (STM32_USB_OTG_FS_NUM_EP) -#elif defined(STM32_USB_OTG_HS_ENABLED) -#define _TOTAL_NUM_ENDPOINTS (STM32_USB_OTG_HS_NUM_EP) +#ifdef MCU_ESP32 + +#include "esp_err.h" +#include "esp_intr_alloc.h" +#include "esp_private/usb_phy.h" +#include "soc/soc_caps.h" + +#endif + +#if defined(DWC2_USB_OTG_FS_ENABLED) && defined(DWC2_USB_OTG_HS_ENABLED) +#define _TOTAL_NUM_ENDPOINTS (DWC2_USB_OTG_FS_NUM_EP + \ + DWC2_USB_OTG_HS_NUM_EP) +#elif defined(DWC2_USB_OTG_FS_ENABLED) +#define _TOTAL_NUM_ENDPOINTS (DWC2_USB_OTG_FS_NUM_EP) +#elif defined(DWC2_USB_OTG_HS_ENABLED) +#define _TOTAL_NUM_ENDPOINTS (DWC2_USB_OTG_HS_NUM_EP) #endif /* Mask for the set of interrupts used */ -#define STM32_FSHS_USB_GINT_MASK \ +#define DWC2_FSHS_USB_GINT_MASK \ (USB_OTG_GINTMSK_USBSUSPM | \ USB_OTG_GINTMSK_WUIM | \ USB_OTG_GINTMSK_ENUMDNEM | \ @@ -62,11 +88,11 @@ USB_OTG_GINTMSK_OEPINT | \ USB_OTG_GINTMSK_RXFLVLM) -#define STM32_PKTSTS_GONAK 0x01 /**< Rx fifo global out nak */ -#define STM32_PKTSTS_DATA_UPDT 0x02 /**< Rx fifo data update */ -#define STM32_PKTSTS_XFER_COMP 0x03 /**< Rx fifo data complete */ -#define STM32_PKTSTS_SETUP_COMP 0x04 /**< Rx fifo setup complete */ -#define STM32_PKTSTS_SETUP_UPDT 0x06 /**< Rx fifo setup update */ +#define DWC2_PKTSTS_GONAK 0x01 /**< Rx fifo global out nak */ +#define DWC2_PKTSTS_DATA_UPDT 0x02 /**< Rx fifo data update */ +#define DWC2_PKTSTS_XFER_COMP 0x03 /**< Rx fifo data complete */ +#define DWC2_PKTSTS_SETUP_COMP 0x04 /**< Rx fifo setup complete */ +#define DWC2_PKTSTS_SETUP_UPDT 0x06 /**< Rx fifo setup update */ /* Some device families (F7 and L4) forgot to define the FS device FIFO size * * in their vendor headers. This define sets it to the value from the * @@ -83,51 +109,71 @@ #endif /* minimum depth of an individual transmit FIFO */ -#define STM32_USB_OTG_FIFO_MIN_WORD_SIZE (16U) +#define DWC2_USB_OTG_FIFO_MIN_WORD_SIZE (16U) /* Offset for OUT endpoints in a shared IN/OUT endpoint bit flag register */ -#define STM32_USB_OTG_REG_EP_OUT_OFFSET (16U) +#define DWC2_USB_OTG_REG_EP_OUT_OFFSET (16U) /* Endpoint zero size values */ -#define STM32_USB_OTG_EP0_SIZE_64 (0x0) -#define STM32_USB_OTG_EP0_SIZE_32 (0x1) -#define STM32_USB_OTG_EP0_SIZE_16 (0x2) -#define STM32_USB_OTG_EP0_SIZE_8 (0x3) +#define DWC2_USB_OTG_EP0_SIZE_64 (0x0) +#define DWC2_USB_OTG_EP0_SIZE_32 (0x1) +#define DWC2_USB_OTG_EP0_SIZE_16 (0x2) +#define DWC2_USB_OTG_EP0_SIZE_8 (0x3) /* Endpoint type values */ -#define STM32_USB_OTG_EP_TYPE_CONTROL (0x00 << USB_OTG_DOEPCTL_EPTYP_Pos) -#define STM32_USB_OTG_EP_TYPE_ISO (0x01 << USB_OTG_DOEPCTL_EPTYP_Pos) -#define STM32_USB_OTG_EP_TYPE_BULK (0x02 << USB_OTG_DOEPCTL_EPTYP_Pos) -#define STM32_USB_OTG_EP_TYPE_INTERRUPT (0x03 << USB_OTG_DOEPCTL_EPTYP_Pos) +#define DWC2_USB_OTG_EP_TYPE_CONTROL (0x00 << USB_OTG_DOEPCTL_EPTYP_Pos) +#define DWC2_USB_OTG_EP_TYPE_ISO (0x01 << USB_OTG_DOEPCTL_EPTYP_Pos) +#define DWC2_USB_OTG_EP_TYPE_BULK (0x02 << USB_OTG_DOEPCTL_EPTYP_Pos) +#define DWC2_USB_OTG_EP_TYPE_INTERRUPT (0x03 << USB_OTG_DOEPCTL_EPTYP_Pos) + +/** + * @brief DWC2 USB OTG peripheral device out endpoint struct + */ +typedef struct { + usbdev_ep_t ep; /**< Inherited usbdev endpoint struct */ + uint8_t *out_buf; /**< Requested data output buffer */ +} dwc2_usb_otg_fshs_out_ep_t; + +/** + * @brief DWC2 USB OTG peripheral device context + */ +typedef struct { + usbdev_t usbdev; /**< Inherited usbdev struct */ + const dwc2_usb_otg_fshs_config_t *config; /**< USB peripheral config */ + size_t fifo_pos; /**< FIFO space occupied */ + usbdev_ep_t *in; /**< In endpoints */ + dwc2_usb_otg_fshs_out_ep_t *out; /**< Out endpoints */ + bool suspend; /**< Suspend status */ +} dwc2_usb_otg_fshs_t; /* List of instantiated USB peripherals */ -static stm32_usb_otg_fshs_t _usbdevs[USBDEV_NUMOF] = { 0 }; +static dwc2_usb_otg_fshs_t _usbdevs[USBDEV_NUMOF] = { 0 }; -static stm32_usb_otg_fshs_out_ep_t _out[_TOTAL_NUM_ENDPOINTS]; +static dwc2_usb_otg_fshs_out_ep_t _out[_TOTAL_NUM_ENDPOINTS]; static usbdev_ep_t _in[_TOTAL_NUM_ENDPOINTS]; /* Forward declaration for the usb device driver */ const usbdev_driver_t driver; -static void _flush_tx_fifo(const stm32_usb_otg_fshs_config_t *conf, +static void _flush_tx_fifo(const dwc2_usb_otg_fshs_config_t *conf, uint8_t fifo_num); /************************************************************************* * Conversion function from the base address to specific register blocks * *************************************************************************/ static USB_OTG_GlobalTypeDef *_global_regs( - const stm32_usb_otg_fshs_config_t *conf) + const dwc2_usb_otg_fshs_config_t *conf) { return (USB_OTG_GlobalTypeDef *)(conf->periph + USB_OTG_GLOBAL_BASE); } static USB_OTG_DeviceTypeDef *_device_regs( - const stm32_usb_otg_fshs_config_t *conf) + const dwc2_usb_otg_fshs_config_t *conf) { return (USB_OTG_DeviceTypeDef *)(conf->periph + USB_OTG_DEVICE_BASE); } static USB_OTG_INEndpointTypeDef *_in_regs( - const stm32_usb_otg_fshs_config_t *conf, + const dwc2_usb_otg_fshs_config_t *conf, size_t endpoint) { return (USB_OTG_INEndpointTypeDef *)(conf->periph + @@ -136,7 +182,7 @@ static USB_OTG_INEndpointTypeDef *_in_regs( } static USB_OTG_OUTEndpointTypeDef *_out_regs( - const stm32_usb_otg_fshs_config_t *conf, + const dwc2_usb_otg_fshs_config_t *conf, size_t endpoint) { return (USB_OTG_OUTEndpointTypeDef *)(conf->periph + @@ -144,12 +190,12 @@ static USB_OTG_OUTEndpointTypeDef *_out_regs( USB_OTG_EP_REG_SIZE * endpoint); } -static __I uint32_t *_rx_fifo(const stm32_usb_otg_fshs_config_t *conf) +static __I uint32_t *_rx_fifo(const dwc2_usb_otg_fshs_config_t *conf) { return (__I uint32_t *)(conf->periph + USB_OTG_FIFO_BASE); } -static __O uint32_t *_tx_fifo(const stm32_usb_otg_fshs_config_t *conf, +static __O uint32_t *_tx_fifo(const dwc2_usb_otg_fshs_config_t *conf, size_t num) { return (__O uint32_t *)(conf->periph + @@ -157,7 +203,7 @@ static __O uint32_t *_tx_fifo(const stm32_usb_otg_fshs_config_t *conf, USB_OTG_FIFO_SIZE * num); } -static __IO uint32_t *_pcgcctl_reg(const stm32_usb_otg_fshs_config_t *conf) +static __IO uint32_t *_pcgcctl_reg(const dwc2_usb_otg_fshs_config_t *conf) { return (__IO uint32_t *)(conf->periph + USB_OTG_PCGCCTL_BASE); } @@ -169,25 +215,25 @@ static __IO uint32_t *_pcgcctl_reg(const stm32_usb_otg_fshs_config_t *conf) * * @param config configuration struct */ -static size_t _max_endpoints(const stm32_usb_otg_fshs_config_t *config) +static size_t _max_endpoints(const dwc2_usb_otg_fshs_config_t *config) { - return (config->type == STM32_USB_OTG_FS) ? - STM32_USB_OTG_FS_NUM_EP : - STM32_USB_OTG_HS_NUM_EP; + return (config->type == DWC2_USB_OTG_FS) ? + DWC2_USB_OTG_FS_NUM_EP : + DWC2_USB_OTG_HS_NUM_EP; } -static bool _uses_dma(const stm32_usb_otg_fshs_config_t *config) +static bool _uses_dma(const dwc2_usb_otg_fshs_config_t *config) { -#if defined(STM32_USB_OTG_HS_ENABLED) && STM32_USB_OTG_HS_USE_DMA - return config->type == STM32_USB_OTG_HS; +#if defined(DWC2_USB_OTG_HS_ENABLED) && STM32_USB_OTG_HS_USE_DMA + return config->type == DWC2_USB_OTG_HS; #else (void)config; return false; #endif } -static size_t _setup(stm32_usb_otg_fshs_t *usbdev, - const stm32_usb_otg_fshs_config_t *config, size_t idx) +static size_t _setup(dwc2_usb_otg_fshs_t *usbdev, + const dwc2_usb_otg_fshs_config_t *config, size_t idx) { usbdev->usbdev.driver = &driver; usbdev->config = config; @@ -206,7 +252,7 @@ void usbdev_init_lowlevel(void) size_t ep_idx = 0; for (size_t i = 0; i < USBDEV_NUMOF; i++) { - ep_idx += _setup(&_usbdevs[i], &stm32_usb_otg_fshs_config[i], ep_idx); + ep_idx += _setup(&_usbdevs[i], &dwc2_usb_otg_fshs_config[i], ep_idx); } #ifdef NDEBUG (void)ep_idx; @@ -220,7 +266,7 @@ usbdev_t *usbdev_get_ctx(unsigned num) return &_usbdevs[num].usbdev; } -static void _enable_global_out_nak(const stm32_usb_otg_fshs_config_t *conf) +static void _enable_global_out_nak(const dwc2_usb_otg_fshs_config_t *conf) { if (_device_regs(conf)->DCTL & USB_OTG_DCTL_GONSTS) { return; @@ -229,7 +275,7 @@ static void _enable_global_out_nak(const stm32_usb_otg_fshs_config_t *conf) while (!(_device_regs(conf)->DCTL & USB_OTG_DCTL_GONSTS)) {} } -static void _disable_global_out_nak(const stm32_usb_otg_fshs_config_t *conf) +static void _disable_global_out_nak(const dwc2_usb_otg_fshs_config_t *conf) { if (!(_device_regs(conf)->DCTL & USB_OTG_DCTL_GONSTS)) { return; @@ -238,7 +284,7 @@ static void _disable_global_out_nak(const stm32_usb_otg_fshs_config_t *conf) while ((_device_regs(conf)->DCTL & USB_OTG_DCTL_GONSTS)) {} } -static void _enable_global_in_nak(const stm32_usb_otg_fshs_config_t *conf) +static void _enable_global_in_nak(const dwc2_usb_otg_fshs_config_t *conf) { if (_device_regs(conf)->DCTL & USB_OTG_DCTL_GINSTS) { return; @@ -247,7 +293,7 @@ static void _enable_global_in_nak(const stm32_usb_otg_fshs_config_t *conf) while (!(_device_regs(conf)->DCTL & USB_OTG_DCTL_GINSTS)) {} } -static void _disable_global_in_nak(const stm32_usb_otg_fshs_config_t *conf) +static void _disable_global_in_nak(const dwc2_usb_otg_fshs_config_t *conf) { if (!(_device_regs(conf)->DCTL & USB_OTG_DCTL_GINSTS)) { return; @@ -256,7 +302,7 @@ static void _disable_global_in_nak(const stm32_usb_otg_fshs_config_t *conf) while ((_device_regs(conf)->DCTL & USB_OTG_DCTL_GINSTS)) {} } -static void _disable_global_nak(const stm32_usb_otg_fshs_config_t *conf) +static void _disable_global_nak(const dwc2_usb_otg_fshs_config_t *conf) { _disable_global_in_nak(conf); _disable_global_out_nak(conf); @@ -266,13 +312,13 @@ static uint32_t _type_to_reg(usb_ep_type_t type) { switch (type) { case USB_EP_TYPE_CONTROL: - return STM32_USB_OTG_EP_TYPE_CONTROL; + return DWC2_USB_OTG_EP_TYPE_CONTROL; case USB_EP_TYPE_ISOCHRONOUS: - return STM32_USB_OTG_EP_TYPE_ISO; + return DWC2_USB_OTG_EP_TYPE_ISO; case USB_EP_TYPE_BULK: - return STM32_USB_OTG_EP_TYPE_BULK; + return DWC2_USB_OTG_EP_TYPE_BULK; case USB_EP_TYPE_INTERRUPT: - return STM32_USB_OTG_EP_TYPE_INTERRUPT; + return DWC2_USB_OTG_EP_TYPE_INTERRUPT; default: assert(false); return 0; @@ -283,13 +329,13 @@ static uint32_t _ep0_size(size_t size) { switch (size) { case 64: - return STM32_USB_OTG_EP0_SIZE_64; + return DWC2_USB_OTG_EP0_SIZE_64; case 32: - return STM32_USB_OTG_EP0_SIZE_32; + return DWC2_USB_OTG_EP0_SIZE_32; case 16: - return STM32_USB_OTG_EP0_SIZE_16; + return DWC2_USB_OTG_EP0_SIZE_16; case 8: - return STM32_USB_OTG_EP0_SIZE_8; + return DWC2_USB_OTG_EP0_SIZE_8; default: assert(false); return 0x00; @@ -301,10 +347,10 @@ static uint32_t _ep0_size(size_t size) * * Endpoint is only deactivated if it was activated */ -static void _ep_in_disable(const stm32_usb_otg_fshs_config_t *conf, size_t num) +static void _ep_in_disable(const dwc2_usb_otg_fshs_config_t *conf, size_t num) { if (_in_regs(conf, num)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) { - DEBUG("otg_fs: Disabling IN %u\n", num); + DEBUG("usbdev: Disabling EP%u-IN\n", num); /* Enable global nak according to procedure */ _enable_global_in_nak(conf); /* Flush the fifo to clear pending data */ @@ -323,10 +369,10 @@ static void _ep_in_disable(const stm32_usb_otg_fshs_config_t *conf, size_t num) * * Endpoint is only deactivated if it was activated */ -static void _ep_out_disable(const stm32_usb_otg_fshs_config_t *conf, size_t num) +static void _ep_out_disable(const dwc2_usb_otg_fshs_config_t *conf, size_t num) { if (_out_regs(conf, num)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) { - DEBUG("otg_fs: Disabling OUT %u\n", num); + DEBUG("usbdev: Disabling EP%u-OUT\n", num); /* Enable global nak according to procedure */ _enable_global_out_nak(conf); /* No need to flush the fifo here, this works(tm) */ @@ -341,8 +387,8 @@ static void _ep_out_disable(const stm32_usb_otg_fshs_config_t *conf, size_t num) static void _ep_deactivate(usbdev_ep_t *ep) { - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)ep->dev; - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)ep->dev; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; if (ep->dir == USB_EP_DIR_IN) { _ep_in_disable(conf, ep->num); @@ -356,8 +402,8 @@ static void _ep_deactivate(usbdev_ep_t *ep) static void _ep_activate(usbdev_ep_t *ep) { - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)ep->dev; - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)ep->dev; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; if (ep->dir == USB_EP_DIR_IN) { _ep_in_disable(conf, ep->num); @@ -378,7 +424,7 @@ static void _ep_activate(usbdev_ep_t *ep) else { _ep_out_disable(conf, ep->num); _device_regs(conf)->DAINTMSK |= - 1 << (ep->num + STM32_USB_OTG_REG_EP_OUT_OFFSET); + 1 << (ep->num + DWC2_USB_OTG_REG_EP_OUT_OFFSET); _out_regs(conf, ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK | USB_OTG_DOEPCTL_USBAEP; _type_to_reg(ep->type); @@ -392,63 +438,63 @@ static void _ep_activate(usbdev_ep_t *ep) } } -static inline void _usb_attach(stm32_usb_otg_fshs_t *usbdev) +static inline void _usb_attach(dwc2_usb_otg_fshs_t *usbdev) { - DEBUG("otg_fs: Attaching to host\n"); + DEBUG("usbdev: Attaching to host\n"); /* Disable the soft disconnect feature */ _device_regs(usbdev->config)->DCTL &= ~USB_OTG_DCTL_SDIS; } -static inline void _usb_detach(stm32_usb_otg_fshs_t *usbdev) +static inline void _usb_detach(dwc2_usb_otg_fshs_t *usbdev) { - DEBUG("otg_fs: Detaching from host\n"); + DEBUG("usbdev: Detaching from host\n"); /* Enable the soft disconnect feature */ _device_regs(usbdev->config)->DCTL |= USB_OTG_DCTL_SDIS; } -static void _set_address(stm32_usb_otg_fshs_t *usbdev, uint8_t address) +static void _set_address(dwc2_usb_otg_fshs_t *usbdev, uint8_t address) { _device_regs(usbdev->config)->DCFG = (_device_regs(usbdev->config)->DCFG & ~(USB_OTG_DCFG_DAD_Msk)) | (address << USB_OTG_DCFG_DAD_Pos); } -static usbdev_ep_t *_get_ep(stm32_usb_otg_fshs_t *usbdev, unsigned num, +static usbdev_ep_t *_get_ep(dwc2_usb_otg_fshs_t *usbdev, unsigned num, usb_ep_dir_t dir) { - if (num >= STM32_USB_OTG_FS_NUM_EP) { + if (num >= DWC2_USB_OTG_FS_NUM_EP) { return NULL; } return dir == USB_EP_DIR_IN ? &usbdev->in[num] : &usbdev->out[num].ep; } #if defined(DEVELHELP) && !defined(NDEBUG) -static size_t _total_fifo_size(const stm32_usb_otg_fshs_config_t *conf) +static size_t _total_fifo_size(const dwc2_usb_otg_fshs_config_t *conf) { - if (conf->type == STM32_USB_OTG_FS) { -#ifdef STM32_USB_OTG_FS_ENABLED + if (conf->type == DWC2_USB_OTG_FS) { +#ifdef DWC2_USB_OTG_FS_ENABLED return USB_OTG_FS_TOTAL_FIFO_SIZE; #else return 0; -#endif /* STM32_USB_OTG_FS_ENABLED */ +#endif /* DWC2_USB_OTG_FS_ENABLED */ } else { -#ifdef STM32_USB_OTG_HS_ENABLED +#ifdef DWC2_USB_OTG_HS_ENABLED return USB_OTG_HS_TOTAL_FIFO_SIZE; #else return 0; -#endif /* STM32_USB_OTG_HS_ENABLED */ +#endif /* DWC2_USB_OTG_HS_ENABLED */ } } #endif /* defined(DEVELHELP) && !defined(NDEBUG) */ -static void _configure_tx_fifo(stm32_usb_otg_fshs_t *usbdev, size_t num, +static void _configure_tx_fifo(dwc2_usb_otg_fshs_t *usbdev, size_t num, size_t len) { /* TX Fifo size must be at least 16 words long and must be word aligned */ - size_t wordlen = len < (STM32_USB_OTG_FIFO_MIN_WORD_SIZE * sizeof(uint32_t)) - ? STM32_USB_OTG_FIFO_MIN_WORD_SIZE + size_t wordlen = len < (DWC2_USB_OTG_FIFO_MIN_WORD_SIZE * sizeof(uint32_t)) + ? DWC2_USB_OTG_FIFO_MIN_WORD_SIZE : (len + (sizeof(uint32_t) - 1)) / sizeof(uint32_t); /* Check max size */ @@ -463,27 +509,27 @@ static void _configure_tx_fifo(stm32_usb_otg_fshs_t *usbdev, size_t num, usbdev->fifo_pos += wordlen; } -static void _configure_fifo(stm32_usb_otg_fshs_t *usbdev) +static void _configure_fifo(dwc2_usb_otg_fshs_t *usbdev) { /* TODO: cleanup, more dynamic, etc */ - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; - size_t rx_size = conf->type == STM32_USB_OTG_FS - ? STM32_USB_OTG_FS_RX_FIFO_SIZE - : STM32_USB_OTG_HS_RX_FIFO_SIZE; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; + size_t rx_size = conf->type == DWC2_USB_OTG_FS + ? DWC2_USB_OTG_FS_RX_FIFO_SIZE + : DWC2_USB_OTG_HS_RX_FIFO_SIZE; _global_regs(conf)->GRXFSIZ = (_global_regs(conf)->GRXFSIZ & ~USB_OTG_GRXFSIZ_RXFD) | rx_size; _global_regs(conf)->DIEPTXF0_HNPTXFSIZ = - (STM32_USB_OTG_FIFO_MIN_WORD_SIZE << USB_OTG_TX0FD_Pos) | + (DWC2_USB_OTG_FIFO_MIN_WORD_SIZE << USB_OTG_TX0FD_Pos) | rx_size; - usbdev->fifo_pos = (rx_size + STM32_USB_OTG_FIFO_MIN_WORD_SIZE); + usbdev->fifo_pos = (rx_size + DWC2_USB_OTG_FIFO_MIN_WORD_SIZE); } static usbdev_ep_t *_usbdev_new_ep(usbdev_t *dev, usb_ep_type_t type, usb_ep_dir_t dir, size_t len) { - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)dev; + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)dev; usbdev_ep_t *ep = NULL; if (type == USB_EP_TYPE_CONTROL) { @@ -497,7 +543,7 @@ static usbdev_ep_t *_usbdev_new_ep(usbdev_t *dev, usb_ep_type_t type, } else { /* Find the first unassigned ep with matching direction */ - for (unsigned idx = 1; idx < STM32_USB_OTG_FS_NUM_EP && !ep; idx++) { + for (unsigned idx = 1; idx < DWC2_USB_OTG_FS_NUM_EP && !ep; idx++) { usbdev_ep_t *candidate_ep = _get_ep(usbdev, idx, dir); if (candidate_ep->type == USB_EP_TYPE_NONE) { ep = candidate_ep; @@ -524,7 +570,7 @@ static usbdev_ep_t *_usbdev_new_ep(usbdev_t *dev, usb_ep_type_t type, * @param conf usbdev context * @param fifo_num fifo number to reset, 0x10 for all fifos */ -static void _flush_tx_fifo(const stm32_usb_otg_fshs_config_t *conf, +static void _flush_tx_fifo(const dwc2_usb_otg_fshs_config_t *conf, uint8_t fifo_num) { uint32_t reg = _global_regs(conf)->GRSTCTL & ~(USB_OTG_GRSTCTL_TXFNUM); @@ -535,13 +581,13 @@ static void _flush_tx_fifo(const stm32_usb_otg_fshs_config_t *conf, while (_global_regs(conf)->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) {} } -static void _flush_rx_fifo(const stm32_usb_otg_fshs_config_t *conf) +static void _flush_rx_fifo(const dwc2_usb_otg_fshs_config_t *conf) { _global_regs(conf)->GRSTCTL |= USB_OTG_GRSTCTL_RXFFLSH; while (_global_regs(conf)->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) {} } -static void _sleep_periph(const stm32_usb_otg_fshs_config_t *conf) +static void _sleep_periph(const dwc2_usb_otg_fshs_config_t *conf) { *_pcgcctl_reg(conf) |= USB_OTG_PCGCCTL_STOPCLK; /* Unblocking STM32_PM_STOP during suspend on the stm32f446 breaks @@ -552,7 +598,7 @@ static void _sleep_periph(const stm32_usb_otg_fshs_config_t *conf) #endif } -static void _wake_periph(const stm32_usb_otg_fshs_config_t *conf) +static void _wake_periph(const dwc2_usb_otg_fshs_config_t *conf) { #ifdef STM32_USB_OTG_CID_1x pm_block(STM32_PM_STOP); @@ -562,9 +608,9 @@ static void _wake_periph(const stm32_usb_otg_fshs_config_t *conf) _flush_tx_fifo(conf, 0x10); } -static void _reset_eps(stm32_usb_otg_fshs_t *usbdev) +static void _reset_eps(dwc2_usb_otg_fshs_t *usbdev) { - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; /* Set the NAK for all endpoints */ for (size_t i = 0; i < _max_endpoints(conf); i++) { @@ -574,9 +620,9 @@ static void _reset_eps(stm32_usb_otg_fshs_t *usbdev) } } -static void _reset_periph(stm32_usb_otg_fshs_t *usbdev) +static void _reset_periph(dwc2_usb_otg_fshs_t *usbdev) { - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; /* Wait for AHB idle */ while (!(_global_regs(conf)->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL)) {} @@ -585,7 +631,8 @@ static void _reset_periph(stm32_usb_otg_fshs_t *usbdev) while (_global_regs(conf)->GRSTCTL & USB_OTG_GRSTCTL_CSRST) {} } -static void _enable_gpio(const stm32_usb_otg_fshs_config_t *conf) +#ifdef MCU_STM32 +static void _enable_gpio(const dwc2_usb_otg_fshs_config_t *conf) { /* Enables clock on the GPIO bus */ gpio_init(conf->dp, GPIO_IN); @@ -594,10 +641,11 @@ static void _enable_gpio(const stm32_usb_otg_fshs_config_t *conf) gpio_init_af(conf->dp, conf->af); gpio_init_af(conf->dm, conf->af); } +#endif -static void _set_mode_device(stm32_usb_otg_fshs_t *usbdev) +static void _set_mode_device(dwc2_usb_otg_fshs_t *usbdev) { - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; /* Force device mode */ _global_regs(conf)->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; @@ -608,32 +656,48 @@ static void _set_mode_device(stm32_usb_otg_fshs_t *usbdev) static void _usbdev_init(usbdev_t *dev) { + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)dev; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; + +#if defined(MCU_STM32) /* Block both STOP and STANDBY, STOP is unblocked during USB suspend * status */ pm_block(STM32_PM_STOP); pm_block(STM32_PM_STANDBY); - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)dev; - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; - #if defined(PWR_CR2_USV) /* on L4 */ /* Validate USB Supply */ PWR->CR2 |= PWR_CR2_USV; -#endif +#endif /* PWR_CR2_USV */ /* Enable the clock to the peripheral */ periph_clk_en(conf->ahb, conf->rcc_mask); _enable_gpio(conf); +#elif defined(MCU_ESP32) + usb_phy_handle_t phy_hdl; /* only needed temporarily */ + + usb_phy_config_t phy_conf = { + .controller = USB_PHY_CTRL_OTG, + .otg_mode = USB_OTG_MODE_DEVICE, + .target = USB_PHY_TARGET_INT, /* only internal PHY supported */ + }; + + if (usb_new_phy(&phy_conf, &phy_hdl) != ESP_OK) { + LOG_ERROR("usbdev: Install USB PHY failed\n"); + } +#else +#error "MCU not supported" +#endif /* TODO: implement ULPI mode when a board is available */ -#ifdef STM32_USB_OTG_HS_ENABLED - if (conf->type == STM32_USB_OTG_HS) { +#ifdef DWC2_USB_OTG_HS_ENABLED + if (conf->type == DWC2_USB_OTG_HS) { /* Disable the ULPI clock in low power mode, this is essential for the * peripheral when using the built-in phy */ periph_lpclk_dis(conf->ahb, RCC_AHB1LPENR_OTGHSULPILPEN); /* Only the built-in phy supported for now */ - assert(conf->phy == STM32_USB_OTG_PHY_BUILTIN); + assert(conf->phy == DWC2_USB_OTG_PHY_BUILTIN); _global_regs(conf)->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; } #endif @@ -647,12 +711,12 @@ static void _usbdev_init(usbdev_t *dev) /* Force the peripheral to device mode */ _set_mode_device(usbdev); - /* Disable Vbus detection and force the pull-up on */ -#ifdef STM32_USB_OTG_CID_1x + /* Disable Vbus detection and force the pull-up on, GCCFG is STM32 specific */ +#if defined(STM32_USB_OTG_CID_1x) /* Enable no Vbus sensing and enable 'Power Down Disable */ _global_regs(usbdev->config)->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS | USB_OTG_GCCFG_PWRDWN; -#else +#elif defined(STM32_USB_OTG_CID_2x) /* Enable no Vbus Detect enable and enable 'Power Down Disable */ _global_regs(usbdev->config)->GCCFG |= USB_OTG_GCCFG_VBDEN | USB_OTG_GCCFG_PWRDWN; @@ -661,7 +725,16 @@ static void _usbdev_init(usbdev_t *dev) USB_OTG_GOTGCTL_VBVALOEN | USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL; +#elif defined(MCU_ESP32) + /* Force Vbus Detect values and ID detect values to device mode */ + _global_regs(usbdev->config)->GOTGCTL |= USB_OTG_GOTGCTL_VBVALOVAL | + USB_OTG_GOTGCTL_VBVALOEN | + USB_OTG_GOTGCTL_BVALOEN | + USB_OTG_GOTGCTL_BVALOVAL; +#else +#error "MCU not supported" #endif + /* disable fancy USB features */ _global_regs(conf)->GUSBCFG &= ~(USB_OTG_GUSBCFG_HNPCAP | USB_OTG_GUSBCFG_SRPCAP); @@ -679,7 +752,7 @@ static void _usbdev_init(usbdev_t *dev) /* Values from the reference manual tables on TRDT configuration * * 0x09 for 24Mhz ABH frequency, 0x06 for 32Mhz or higher AHB frequency */ - uint8_t trdt = conf->type == STM32_USB_OTG_FS ? 0x06 : 0x09; + uint8_t trdt = conf->type == DWC2_USB_OTG_FS ? 0x06 : 0x09; _global_regs(conf)->GUSBCFG = (_global_regs(conf)->GUSBCFG & ~USB_OTG_GUSBCFG_TRDT) | (trdt << USB_OTG_GUSBCFG_TRDT_Pos); @@ -704,10 +777,10 @@ static void _usbdev_init(usbdev_t *dev) } /* Clear the interrupt flags and unmask those interrupts */ - _global_regs(conf)->GINTSTS |= STM32_FSHS_USB_GINT_MASK; - _global_regs(conf)->GINTMSK |= STM32_FSHS_USB_GINT_MASK; + _global_regs(conf)->GINTSTS |= DWC2_FSHS_USB_GINT_MASK; + _global_regs(conf)->GINTMSK |= DWC2_FSHS_USB_GINT_MASK; - DEBUG("otg_fs: USB peripheral currently in %s mode\n", + DEBUG("usbdev: USB peripheral currently in %s mode\n", (_global_regs( conf)->GINTSTS & USB_OTG_GINTSTS_CMOD) ? "host" : "device"); @@ -715,8 +788,16 @@ static void _usbdev_init(usbdev_t *dev) _global_regs(conf)->GAHBCFG |= USB_OTG_GAHBCFG_GINT | USB_OTG_GAHBCFG_TXFELVL; +#if defined(MCU_STM32) /* Unmask the interrupt in the NVIC */ NVIC_EnableIRQ(conf->irqn); +#elif defined(MCU_ESP32) + void isr_otg_fs(void *arg); + /* Allocate the interrupt and connect it with USB interrupt source */ + esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, isr_otg_fs, NULL, NULL); +#else +#error "MCU not supported" +#endif } static int _usbdev_get(usbdev_t *dev, usbopt_t opt, @@ -737,7 +818,7 @@ static int _usbdev_get(usbdev_t *dev, usbopt_t opt, res = sizeof(usb_speed_t); break; default: - DEBUG("otg_fs: Unhandled get call: 0x%x\n", opt); + DEBUG("usbdev: Unhandled get call: 0x%x\n", opt); break; } return res; @@ -748,7 +829,7 @@ static int _usbdev_set(usbdev_t *dev, usbopt_t opt, { (void)value_len; - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)dev; + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)dev; int res = -ENOTSUP; switch (opt) { @@ -768,7 +849,7 @@ static int _usbdev_set(usbdev_t *dev, usbopt_t opt, res = sizeof(usbopt_enable_t); break; default: - DEBUG("otg_fs: Unhandled set call: 0x%x\n", opt); + DEBUG("usbdev: Unhandled set call: 0x%x\n", opt); break; } return res; @@ -776,8 +857,8 @@ static int _usbdev_set(usbdev_t *dev, usbopt_t opt, static void _usbdev_esr(usbdev_t *dev) { - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)dev; - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)dev; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; uint32_t int_status = _global_regs(conf)->GINTSTS; uint32_t event = 0; @@ -785,18 +866,18 @@ static void _usbdev_esr(usbdev_t *dev) if (int_status & USB_OTG_GINTSTS_ENUMDNE) { event = USB_OTG_GINTSTS_ENUMDNE; /* Reset condition done */ - DEBUG("otg_fs: Reset done\n"); + DEBUG("usbdev: Reset done\n"); usbdev->usbdev.cb(&usbdev->usbdev, USBDEV_EVENT_RESET); } else if (int_status & USB_OTG_GINTSTS_USBRST) { /* Start of reset condition */ event = USB_OTG_GINTSTS_USBRST; - DEBUG("otg_fs: Reset start\n"); + DEBUG("usbdev: Reset start\n"); if (usbdev->suspend) { usbdev->suspend = false; _wake_periph(conf); - DEBUG("otg_fs: PHY SUSP %lx\n", *_pcgcctl_reg(conf)); + DEBUG("usbdev: PHY SUSP %" PRIx32 "\n", *_pcgcctl_reg(conf)); } /* Reset all the things! */ @@ -808,7 +889,7 @@ static void _usbdev_esr(usbdev_t *dev) else if (int_status & USB_OTG_GINTSTS_SRQINT) { /* Reset done */ event = USB_OTG_GINTSTS_SRQINT; - DEBUG("otg_fs: Session request\n"); + DEBUG("usbdev: Session request\n"); } else if (int_status & USB_OTG_GINTSTS_USBSUSP) { event = USB_OTG_GINTSTS_USBSUSP; @@ -835,14 +916,14 @@ static void _usbdev_esr(usbdev_t *dev) static void _usbdev_ep_init(usbdev_ep_t *ep) { - DEBUG("otg_fs: Initializing EP %u, %s\n", ep->num, + DEBUG("usbdev: Initializing EP%u-%s\n", ep->num, ep->dir == USB_EP_DIR_IN ? "IN" : "OUT"); } static size_t _get_available(usbdev_ep_t *ep) { - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)ep->dev; - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)ep->dev; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; return ep->len - (_out_regs(conf, ep->num)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ_Msk); @@ -860,7 +941,7 @@ static int _usbdev_ep_get(usbdev_ep_t *ep, usbopt_ep_t opt, res = sizeof(size_t); break; default: - DEBUG("otg_fs: Unhandled endpoint get call: 0x%x\n", opt); + DEBUG("usbdev: Unhandled endpoint get call: 0x%x\n", opt); break; } return res; @@ -868,8 +949,8 @@ static int _usbdev_ep_get(usbdev_ep_t *ep, usbopt_ep_t opt, static void _ep_set_stall(usbdev_ep_t *ep, bool enable) { - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)ep->dev; - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)ep->dev; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; (void)enable; @@ -907,7 +988,7 @@ static int _usbdev_ep_set(usbdev_ep_t *ep, usbopt_ep_t opt, res = sizeof(usbopt_enable_t); break; default: - DEBUG("otg_fs: Unhandled endpoint set call: 0x%x\n", opt); + DEBUG("usbdev: Unhandled endpoint set call: 0x%x\n", opt); break; } return res; @@ -915,10 +996,13 @@ static int _usbdev_ep_set(usbdev_ep_t *ep, usbopt_ep_t opt, static int _usbdev_ep_xmit(usbdev_ep_t *ep, uint8_t *buf, size_t len) { - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)ep->dev; - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; - /* Assert the alignment required for the buffers */ - assert(HAS_ALIGNMENT_OF(buf, USBDEV_CPU_DMA_ALIGNMENT)); + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)ep->dev; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; + + if (_uses_dma(conf)) { + /* Assert the alignment required for the buffers */ + assert(HAS_ALIGNMENT_OF(buf, USBDEV_CPU_DMA_ALIGNMENT)); + } if (ep->dir == USB_EP_DIR_IN) { /* Abort when the endpoint is not active, prevents hangs, @@ -980,7 +1064,7 @@ static int _usbdev_ep_xmit(usbdev_ep_t *ep, uint8_t *buf, size_t len) _out_regs(conf, ep->num)->DOEPDMA = (uint32_t)(intptr_t)buf; } else { - container_of(ep, stm32_usb_otg_fshs_out_ep_t, ep)->out_buf = buf; + container_of(ep, dwc2_usb_otg_fshs_out_ep_t, ep)->out_buf = buf; } /* Configure to receive one packet with ep->len as max length */ @@ -996,7 +1080,7 @@ static int _usbdev_ep_xmit(usbdev_ep_t *ep, uint8_t *buf, size_t len) return 0; } -static void _copy_rxfifo(stm32_usb_otg_fshs_t *usbdev, uint8_t *buf, size_t len) +static void _copy_rxfifo(dwc2_usb_otg_fshs_t *usbdev, uint8_t *buf, size_t len) { /* The FIFO requires 32 bit word reads/writes. This is only called with * usbdev_ep_t::buf, which is aligned to four bytes in _usbdev_new_ep() */ @@ -1009,10 +1093,10 @@ static void _copy_rxfifo(stm32_usb_otg_fshs_t *usbdev, uint8_t *buf, size_t len) } } -static void _read_packet(stm32_usb_otg_fshs_out_ep_t *st_ep) +static void _read_packet(dwc2_usb_otg_fshs_out_ep_t *st_ep) { - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)st_ep->ep.dev; - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)st_ep->ep.dev; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; /* Pop status from the receive fifo status register */ uint32_t status = _global_regs(conf)->GRXSTSP; @@ -1024,10 +1108,10 @@ static void _read_packet(stm32_usb_otg_fshs_out_ep_t *st_ep) /* Packet is copied on the update status and copied on the transfer * complete status*/ - if (pkt_status == STM32_PKTSTS_DATA_UPDT || - pkt_status == STM32_PKTSTS_SETUP_UPDT) { + if (pkt_status == DWC2_PKTSTS_DATA_UPDT || + pkt_status == DWC2_PKTSTS_SETUP_UPDT) { _copy_rxfifo(usbdev, st_ep->out_buf, len); -#ifdef STM32_USB_OTG_CID_2x +#if defined(STM32_USB_OTG_CID_2x) || defined(MCU_ESP32) /* CID 2x doesn't signal SETUP_COMP on non-zero length packets, signal * the TR_COMPLETE event immediately */ if (st_ep->ep.num == 0 && len) { @@ -1037,8 +1121,8 @@ static void _read_packet(stm32_usb_otg_fshs_out_ep_t *st_ep) } /* On zero length frames, only the COMP status is signalled and the UPDT * status is skipped */ - else if (pkt_status == STM32_PKTSTS_XFER_COMP || - pkt_status == STM32_PKTSTS_SETUP_COMP) { + else if (pkt_status == DWC2_PKTSTS_XFER_COMP || + pkt_status == DWC2_PKTSTS_SETUP_COMP) { usbdev->usbdev.epcb(&st_ep->ep, USBDEV_EVENT_TR_COMPLETE); } } @@ -1049,8 +1133,8 @@ static void _read_packet(stm32_usb_otg_fshs_out_ep_t *st_ep) */ static void _usbdev_ep_esr(usbdev_ep_t *ep) { - stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)ep->dev; - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + dwc2_usb_otg_fshs_t *usbdev = (dwc2_usb_otg_fshs_t *)ep->dev; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; if (ep->dir == USB_EP_DIR_IN) { uint32_t status = _in_regs(conf, ep->num)->DIEPINT; @@ -1074,7 +1158,7 @@ static void _usbdev_ep_esr(usbdev_ep_t *ep) if ((_global_regs(conf)->GINTSTS & USB_OTG_GINTSTS_RXFLVL) && (_global_regs(conf)->GRXSTSR & USB_OTG_GRXSTSP_EPNUM_Msk) == ep->num && !_uses_dma(conf)) { - _read_packet(container_of(ep, stm32_usb_otg_fshs_out_ep_t, ep)); + _read_packet(container_of(ep, dwc2_usb_otg_fshs_out_ep_t, ep)); } /* Transfer complete seems only reliable when used with DMA */ else if (_out_regs(conf, ep->num)->DOEPINT & USB_OTG_DOEPINT_XFRC) { @@ -1088,17 +1172,17 @@ static void _usbdev_ep_esr(usbdev_ep_t *ep) _global_regs(conf)->GAHBCFG |= USB_OTG_GAHBCFG_GINT; } -static void _isr_ep(stm32_usb_otg_fshs_t *usbdev) +static void _isr_ep(dwc2_usb_otg_fshs_t *usbdev) { - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; /* Top 16 bits of the register is OUT endpoints, bottom 16 is IN * endpoints */ uint32_t active_ep = _device_regs(conf)->DAINT; if (active_ep) { unsigned epnum = bitarithm_lsb(active_ep); - if (epnum >= STM32_USB_OTG_REG_EP_OUT_OFFSET) { - usbdev->usbdev.epcb(&usbdev->out[epnum - STM32_USB_OTG_REG_EP_OUT_OFFSET].ep, + if (epnum >= DWC2_USB_OTG_REG_EP_OUT_OFFSET) { + usbdev->usbdev.epcb(&usbdev->out[epnum - DWC2_USB_OTG_REG_EP_OUT_OFFSET].ep, USBDEV_EVENT_ESR); } else { @@ -1107,9 +1191,9 @@ static void _isr_ep(stm32_usb_otg_fshs_t *usbdev) } } -void _isr_common(stm32_usb_otg_fshs_t *usbdev) +void _isr_common(dwc2_usb_otg_fshs_t *usbdev) { - const stm32_usb_otg_fshs_config_t *conf = usbdev->config; + const dwc2_usb_otg_fshs_config_t *conf = usbdev->config; uint32_t status = _global_regs(conf)->GINTSTS; @@ -1129,28 +1213,62 @@ void _isr_common(stm32_usb_otg_fshs_t *usbdev) } _global_regs(conf)->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; } +#ifdef MCU_STM32 cortexm_isr_end(); +#endif } -#ifdef STM32_USB_OTG_FS_ENABLED +#if defined(MCU_STM32) + +#ifdef DWC2_USB_OTG_FS_ENABLED void isr_otg_fs(void) { /* Take the first device from the list */ - stm32_usb_otg_fshs_t *usbdev = &_usbdevs[0]; + dwc2_usb_otg_fshs_t *usbdev = &_usbdevs[0]; _isr_common(usbdev); } -#endif /* STM32_USB_OTG_FS_ENABLED */ +#endif /* DWC2_USB_OTG_FS_ENABLED */ -#ifdef STM32_USB_OTG_HS_ENABLED +#ifdef DWC2_USB_OTG_HS_ENABLED void isr_otg_hs(void) { /* Take the last usbdev device from the list */ - stm32_usb_otg_fshs_t *usbdev = &_usbdevs[USBDEV_NUMOF - 1]; + dwc2_usb_otg_fshs_t *usbdev = &_usbdevs[USBDEV_NUMOF - 1]; _isr_common(usbdev); } -#endif /* STM32_USB_OTG_HS_ENABLED */ +#endif /* DWC2_USB_OTG_HS_ENABLED */ + +#elif defined(MCU_ESP32) + +#ifdef DWC2_USB_OTG_FS_ENABLED +void isr_otg_fs(void *arg) +{ + (void)arg; + + /* Take the first device from the list */ + dwc2_usb_otg_fshs_t *usbdev = &_usbdevs[0]; + + _isr_common(usbdev); +} +#endif /* ESP32_USB_OTG_FS_ENABLED */ + +#ifdef DWC2_USB_OTG_HS_ENABLED +void isr_otg_hs(void *arg) +{ + (void)arg; + + /* Take the last usbdev device from the list */ + dwc2_usb_otg_fshs_t *usbdev = &_usbdevs[USBDEV_NUMOF - 1]; + + _isr_common(usbdev); +} +#endif /* ESP32_USB_OTG_HS_ENABLED */ + +#else +#error "MCU not supported" +#endif const usbdev_driver_t driver = { .init = _usbdev_init,