mirror of
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boards/lobaro-lorabox: Add initial support for Lobaro Lorabox board
This commit is contained in:
Leandro Lanzieri
parent
bd1b309c39
commit
177ef5bfa9
3
boards/lobaro-lorabox/Makefile
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3
boards/lobaro-lorabox/Makefile
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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3
boards/lobaro-lorabox/Makefile.dep
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3
boards/lobaro-lorabox/Makefile.dep
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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9
boards/lobaro-lorabox/Makefile.features
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9
boards/lobaro-lorabox/Makefile.features
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@ -0,0 +1,9 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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-include $(RIOTCPU)/stm32l1/Makefile.features
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26
boards/lobaro-lorabox/Makefile.include
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26
boards/lobaro-lorabox/Makefile.include
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@ -0,0 +1,26 @@
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## the cpu to build for
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export CPU = stm32l1
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export CPU_MODEL = stm32l151cb
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# add the common header files to the include path
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INCLUDES += -I$(RIOTBOARD)/lobaro-lorabox/include
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# configure the serial terminal
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PORT_LINUX ?= /dev/ttyUSB0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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# setup serial terminal
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include $(RIOTMAKE)/tools/serial.inc.mk
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FLASHER = $(RIOTTOOLS)/stm32loader/stm32loader.py
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# needed for now so the build system generates the .bin file
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HEXFILE = $(BINFILE)
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# -e: erase
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# -u: use sector by sector erase
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# -S: swap RTS and DTR
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# -l 0x1ff: amount of sectors to erase
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FFLAGS += -e -u -S -l 0x1ff -w $(BINFILE)
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TERMFLAGS += --set-rts 0
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29
boards/lobaro-lorabox/board.c
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29
boards/lobaro-lorabox/board.c
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@ -0,0 +1,29 @@
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/*
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* Copyright (C) 2018 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_lobaro_lorabox
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* @{
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*
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* @file
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* @brief Board initialization code for Lobaro LoraBox
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*
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* @author Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
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* @}
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*/
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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/* initialize the CPU */
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cpu_init();
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gpio_init(LED0_PIN, GPIO_OUT);
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gpio_init(EN3V3_PIN, GPIO_OUT);
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}
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91
boards/lobaro-lorabox/doc.txt
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91
boards/lobaro-lorabox/doc.txt
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@ -0,0 +1,91 @@
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/**
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@defgroup boards_lobaro_lorabox Lobaro Lorabox
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@ingroup boards
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@brief Support for the Lobaro LoraBox with stm32l151cb-a
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## Hardware
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### MCU
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| MCU | stm32l151cb-a |
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|:------------- |:--------------------- |
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| Family | ARM Cortex-M3 |
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| Vendor | ST Microelectronics |
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| RAM | 16Kb |
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| Flash | 128Kb |
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| Frequency | 32MHz (no external oscilator connected) |
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| FPU | no |
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| Timers | 10 (8x 16-bit, 2x watchdog timers) |
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| ADCs | 1x 24-channel 12-bit |
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| UARTs | 3 |
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| SPIs | 2 |
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| I2Cs | 2 |
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| Vcc | 1.65V - 3.6V |
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| Datasheet | [Datasheet](https://www.st.com/resource/en/datasheet/stm32l151cb-a.pdf) |
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| Reference Manual | [Reference Manual](https://www.st.com/content/ccc/resource/technical/document/reference_manual/cc/f9/93/b2/f0/82/42/57/CD00240193.pdf/files/CD00240193.pdf/jcr:content/translations/en.CD00240193.pdf) |
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| Programming Manual | [Programming Manual](https://www.st.com/content/ccc/resource/technical/document/programming_manual/5b/ca/8d/83/56/7f/40/08/CD00228163.pdf/files/CD00228163.pdf/jcr:content/translations/en.CD00228163.pdf) |
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| Board Manual | [Board Manual](https://www.lobaro.com/download/7250/)|
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### User Interface
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1 LEDs:
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| NAME | LED0 |
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| ----- | ----- |
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| Color | green |
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| Pin | P1 |
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## Flashing
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### Connections
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To flash using the STM32 ROM bootloader on the board, use the provided UART-USB
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bridge and connect it to the *Config* port. The *Config* port pinout is the
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following:
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```
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--------------- ---------------
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| 1 2 3 4 5 6 | | x x x x x x |
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--------------- ---------------
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Config Addon
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1: RST
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2: VCC
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3: RX1
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4: TX1
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5: Boot0
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6: GND
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```
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### STM32 Loader
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To flash RIOT on the board, after connection the UART-USB bridge, just run:
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```
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BOARD=lobaro-lorabox make flash
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```
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This uses the stm32loader script to erase the memory and flash it interfacing
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with the STM32 ROM bootloader.
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### Lobaro Tool
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Another way of interfacing with the STM32 ROM bootloader is using the **Lobaro Maintenance Tool** provided
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[online](https://www.lobaro.com/lobaro-maintenance-tool/) for free for Linux,
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Mac & Windows. It allows flashing and accessing the UART.
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## Connecting via Serial
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The default UART port is the USART1, the same that is used for flashing, so it
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is available on the *Config* port. The default port is /dev/ttyUSB0. To access
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the port run:
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```
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BOARD=lobaro-lorabox make term
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```
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**Note:** If you want to access the port with a different application please
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keep in mind that RTS must be set to '0' and DTR to '1' as the provided UART-USB
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bridge seems to invert this lines.
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*/
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## SX1272 radio
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Please note that the board has a Semtech SX1272 radio. This means that when the
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semtech-loramac package or the sx127x driver are used the correct driver version
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(sx1272) must be selected.
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92
boards/lobaro-lorabox/include/board.h
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92
boards/lobaro-lorabox/include/board.h
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@ -0,0 +1,92 @@
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/*
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* Copyright (C) 2018 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_lobaro_lorabox
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* @brief Support for Lobaro LoraBox
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* @{
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*
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* @file
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* @brief Common pin definitions and board configuration options
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*
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* @author Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name LED pin definitions and handlers
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* @{
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*/
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#define AUTO_INIT_LED0
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#define LED0_PORT GPIOA
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#define LED0_PIN GPIO_PIN(PORT_A, 1)
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#define LED0_MASK (1 << 1)
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#define LED0_ON (LED0_PORT->BSRR = (LED0_MASK << 16))
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#define LED0_OFF (LED0_PORT->BSRR = LED0_MASK)
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#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
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#define EN3V3_PORT GPIOA
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#define EN3V3_PIN GPIO_PIN(PORT_A, 11)
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#define EN3V3_MASK (1 << 11)
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#define EN3V3_ON (EN3V3_PORT->BSRR = EN3V3_MASK)
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#define EN3V3_OFF (EN3V3_PORT->BSRR = (EN3V3_MASK << 16))
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#define EN3V3_TOGGLE (EN3V3_PORT->ODR ^= EN3V3_MASK)
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/** @} */
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/**
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* @name SX127X
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*
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* SX127X configuration.
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* @{
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*/
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#define SX127X_PARAM_SPI (SPI_DEV(0))
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#define SX127X_PARAM_SPI_NSS GPIO_PIN(PORT_B, 0)
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#define SX127X_PARAM_RESET GPIO_PIN(PORT_A, 4)
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#define SX127X_PARAM_DIO0 GPIO_PIN(PORT_B, 1)
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#define SX127X_PARAM_DIO1 GPIO_PIN(PORT_B, 10)
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#define SX127X_PARAM_DIO2 GPIO_PIN(PORT_B, 11)
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#define SX127X_PARAM_DIO3 GPIO_PIN(PORT_B, 7)
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#define SX127X_PARAM_PASELECT (SX127X_PA_RFO)
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#define SX127X_PARAMS { .spi = SX127X_PARAM_SPI, \
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.nss_pin = SX127X_PARAM_SPI_NSS, \
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.reset_pin = SX127X_PARAM_RESET, \
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.dio0_pin = SX127X_PARAM_DIO0, \
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.dio1_pin = SX127X_PARAM_DIO1, \
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.dio2_pin = SX127X_PARAM_DIO2, \
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.dio3_pin = SX127X_PARAM_DIO3, \
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.paselect = SX127X_PARAM_PASELECT \
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}
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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48
boards/lobaro-lorabox/include/gpio_params.h
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48
boards/lobaro-lorabox/include/gpio_params.h
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/*
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* Copyright (C) 2018 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_lobaro_lorabox
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped GPIOs
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*
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* @author Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief GPIO pin configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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#ifdef AUTO_INIT_LED0
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{
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.name = "LED(green)",
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.pin = LED0_PIN,
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.mode = GPIO_OUT
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},
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#endif
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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232
boards/lobaro-lorabox/include/periph_conf.h
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232
boards/lobaro-lorabox/include/periph_conf.h
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/*
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* Copyright (C) 2014-2016 Freie Universität Berlin
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* 2018 HAW Hamburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_lobaro_lorabox
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* @brief Support for the Lobaro lorabox with stm32l151cb
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the Lobaro lorabox board
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Kevin Weiss <kevin.weiss@haw-hamburg.de>
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* @author Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name xtimer configuration
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* @{
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*/
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#define XTIMER_WIDTH (16)
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#define XTIMER_BACKOFF (50)
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#define XTIMER_ISR_BACKOFF (40)
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/** @} */
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSI (16000000U) /* frequency of internal oscillator */
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#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
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/*
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* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz)
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*/
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (1)
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#endif
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
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#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
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#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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}
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};
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#define TIMER_0_ISR (isr_tim2)
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name Real time counter configuration
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* @{
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*/
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#define RTC_NUMOF (1U)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn
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},
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn
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}
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_1_ISR (isr_usart2)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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#define PWM_NUMOF 0
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 32000000Hz */
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7, /* -> 125000Hz */
|
||||
5, /* -> 500000Hz */
|
||||
4, /* -> 1000000Hz */
|
||||
2, /* -> 4000000Hz */
|
||||
1 /* -> 8000000Hz */
|
||||
},
|
||||
{ /* for APB2 @ 32000000Hz */
|
||||
7, /* -> 125000Hz */
|
||||
5, /* -> 500000Hz */
|
||||
4, /* -> 1000000Hz */
|
||||
2, /* -> 4000000Hz */
|
||||
1 /* -> 8000000Hz */
|
||||
}
|
||||
};
|
||||
|
||||
static const spi_conf_t spi_config[] = {
|
||||
{
|
||||
.dev = SPI1,
|
||||
.mosi_pin = GPIO_PIN(PORT_A, 7),
|
||||
.miso_pin = GPIO_PIN(PORT_A, 6),
|
||||
.sclk_pin = GPIO_PIN(PORT_A, 5),
|
||||
.cs_pin = GPIO_PIN(PORT_B, 0),
|
||||
.af = GPIO_AF5,
|
||||
.rccmask = RCC_APB2ENR_SPI1EN,
|
||||
.apbbus = APB2
|
||||
},
|
||||
{
|
||||
.dev = SPI2,
|
||||
.mosi_pin = GPIO_PIN(PORT_B, 14),
|
||||
.miso_pin = GPIO_PIN(PORT_B, 15),
|
||||
.sclk_pin = GPIO_PIN(PORT_B, 13),
|
||||
.cs_pin = GPIO_PIN(PORT_B, 12),
|
||||
.af = GPIO_AF5,
|
||||
.rccmask = RCC_APB1ENR_SPI2EN,
|
||||
.apbbus = APB1
|
||||
}
|
||||
};
|
||||
|
||||
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C configuration
|
||||
* @{
|
||||
*/
|
||||
static const i2c_conf_t i2c_config[] = {
|
||||
{
|
||||
.dev = I2C1,
|
||||
.speed = I2C_SPEED_NORMAL,
|
||||
.scl_pin = GPIO_PIN(PORT_B, 8),
|
||||
.sda_pin = GPIO_PIN(PORT_B, 9),
|
||||
.scl_af = GPIO_AF4,
|
||||
.sda_af = GPIO_AF4,
|
||||
.bus = APB1,
|
||||
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
||||
.clk = CLOCK_APB1,
|
||||
.irqn = I2C1_EV_IRQn
|
||||
}
|
||||
};
|
||||
|
||||
#define I2C_0_ISR isr_i2c1_ev
|
||||
|
||||
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
* @{
|
||||
*/
|
||||
#define ADC_NUMOF (0U)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name DAC configuration
|
||||
* @{
|
||||
*/
|
||||
#define DAC_NUMOF 0
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CONF_H */
|
||||
/** @} */
|
||||
@ -8,13 +8,14 @@ BOARD ?= native
|
||||
RIOTBASE ?= $(CURDIR)/../..
|
||||
|
||||
BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 bluepill calliope-mini \
|
||||
cc2650-launchpad cc2650stk hifive1 maple-mini \
|
||||
microbit nrf51dongle nrf6310 nucleo-f030r8 nucleo-f070rb \
|
||||
nucleo-f072rb nucleo-f103rb nucleo-f302r8 nucleo-f334r8 nucleo-f410rb \
|
||||
nucleo-l053r8 nucleo-l073rz nucleo-f031k6 nucleo-f042k6 \
|
||||
nucleo-f303k8 nucleo-l031k6 opencm904 \
|
||||
spark-core stm32f0discovery stm32mindev \
|
||||
yunjia-nrf51822
|
||||
cc2650-launchpad cc2650stk hifive1 lobaro-lorabox \
|
||||
maple-mini microbit nrf51dongle nrf6310 \
|
||||
nucleo-f030r8 nucleo-f070rb nucleo-f072rb \
|
||||
nucleo-f103rb nucleo-f302r8 nucleo-f334r8 \
|
||||
nucleo-f410rb nucleo-l053r8 nucleo-l073rz \
|
||||
nucleo-f031k6 nucleo-f042k6 nucleo-f303k8 \
|
||||
nucleo-l031k6 opencm904 spark-core stm32f0discovery \
|
||||
stm32mindev yunjia-nrf51822
|
||||
|
||||
BOARD_BLACKLIST := arduino-duemilanove arduino-mega2560 arduino-uno chronos \
|
||||
msb-430 msb-430h telosb waspmote-pro wsn430-v1_3b \
|
||||
|
||||
@ -16,9 +16,9 @@ BOARD_INSUFFICIENT_MEMORY := bluepill calliope-mini cc2650-launchpad \
|
||||
stm32mindev airfy-beacon arduino-mkr1000 \
|
||||
arduino-mkrfox1200 arduino-mkrzero arduino-zero \
|
||||
b-l072z-lrwan1 cc2538dk ek-lm4f120xl feather-m0 \
|
||||
ikea-tradfri limifrog-v1 mbed_lpc1768 nrf6310 \
|
||||
nucleo-f091rc nucleo-l073rz nz32-sc151 \
|
||||
openmote-cc2538 openmote-b pba-d-01-kw2x \
|
||||
ikea-tradfri limifrog-v1 lobaro-lorabox \
|
||||
mbed_lpc1768 nrf6310 nucleo-f091rc nucleo-l073rz \
|
||||
nz32-sc151 openmote-cc2538 openmote-b pba-d-01-kw2x \
|
||||
remote-pa remote-reva remote-revb samd21-xpro \
|
||||
saml21-xpro samr21-xpro seeeduino_arch-pro \
|
||||
sensebox_samd21 slstk3401a sltb001a slwstk6220a \
|
||||
|
||||
@ -7,12 +7,12 @@ BOARD ?= native
|
||||
RIOTBASE ?= $(CURDIR)/../..
|
||||
|
||||
BOARD_INSUFFICIENT_MEMORY := bluepill calliope-mini cc2650-launchpad \
|
||||
cc2650stk maple-mini microbit nrf51dongle \
|
||||
nucleo-f030r8 nucleo-f031k6 nucleo-f042k6 \
|
||||
nucleo-f070rb nucleo-f072rb nucleo-f103rb \
|
||||
nucleo-f302r8 nucleo-f303k8 nucleo-f334r8 \
|
||||
nucleo-f410rb nucleo-l031k6 nucleo-l053r8 \
|
||||
opencm904 spark-core stm32f0discovery \
|
||||
cc2650stk lobaro-lorabox maple-mini microbit \
|
||||
nrf51dongle nucleo-f030r8 nucleo-f031k6 \
|
||||
nucleo-f042k6 nucleo-f070rb nucleo-f072rb \
|
||||
nucleo-f103rb nucleo-f302r8 nucleo-f303k8 \
|
||||
nucleo-f334r8 nucleo-f410rb nucleo-l031k6 \
|
||||
nucleo-l053r8 opencm904 spark-core stm32f0discovery \
|
||||
stm32mindev
|
||||
|
||||
BOARD_BLACKLIST := arduino-duemilanove arduino-mega2560 arduino-uno \
|
||||
|
||||
@ -21,6 +21,7 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon \
|
||||
feather-m0 \
|
||||
ikea-tradfri \
|
||||
limifrog-v1 maple-mini \
|
||||
lobaro-lorabox \
|
||||
mbed_lpc1768 \
|
||||
mega-xplained \
|
||||
microbit \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user