RIOT/boards/nucleo-f103rb/Makefile.include

# load the common Makefile.include for Nucleo boards
include $(RIOTBOARD)/common/nucleo64/Makefile.include

# On-board debugger uses SWD, so JTAG-only pins PA15, PB3(*), and PB4 can be
# remapped as regular GPIOs instead. (Note: PB3 is also used as SWO. The user
# needs to take care to not enable SWO with the debugger while at the same time
# PB3 is used as GPIO. But RIOT does not use SWO in any case, so if a user adds
# this feature in her/his own code, she/he should be well aware of this.)
CFLAGS += -DSTM32F1_DISABLE_JTAG
boards/nucleo: added and use common board folder 2016-03-11 15:01:58 +01:00			`# load the common Makefile.include for Nucleo boards`
boards/nucleo: factored out nucleo64 common 2017-11-16 17:17:41 +01:00			`include $(RIOTBOARD)/common/nucleo64/Makefile.include`
boards/{nucleo-f103rb,b*pill}: Expose JTAG pins as GPIOs The Nucleo-F103RB comes with an internal SWD programmer/debugger. Thus, the JTAG pins are not going to be used for debugging / programming anyway. The pins are exposed on the headers, so allowing them to be used as GPIOs make a lot of sense. The Bluepill / Blackpill boards only expose the SWD pins on the debug header, but the JTAG pins (not also used by SWD) are exposed on the GPIO pin headers. Hence, exposing them as regular GPIOs seems to be a reasonable choice. 2020-03-08 12:46:07 +01:00
			`# On-board debugger uses SWD, so JTAG-only pins PA15, PB3(*), and PB4 can be`
			`# remapped as regular GPIOs instead. (Note: PB3 is also used as SWO. The user`
			`# needs to take care to not enable SWO with the debugger while at the same time`
			`# PB3 is used as GPIO. But RIOT does not use SWO in any case, so if a user adds`
			`# this feature in her/his own code, she/he should be well aware of this.)`
			`CFLAGS += -DSTM32F1_DISABLE_JTAG`