2022-07-27 16:35:52 +02:00
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/*
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* Copyright (C) 2021 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp32
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* @ingroup drivers_periph_gpio_ll
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* @{
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*
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* @file
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* @brief CPU specific part of the Peripheral GPIO Low-Level API
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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* @}
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*/
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#ifndef GPIO_LL_ARCH_H
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#define GPIO_LL_ARCH_H
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#include "gpio_arch.h"
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2024-04-29 13:32:24 +02:00
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#include "irq.h"
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#include "soc/gpio_reg.h"
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2022-07-27 16:35:52 +02:00
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN /* hide implementation specific details from Doxygen */
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2024-04-29 13:32:24 +02:00
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#define GPIO_PORT(num) (num)
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#if GPIO_PORT_NUMOF > 1
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# define GPIO_PORT_NUM(port) (port)
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#else
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# define GPIO_PORT_NUM(port) 0
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#endif
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2022-07-27 16:35:52 +02:00
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static inline uword_t gpio_ll_read(gpio_port_t port)
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{
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2024-04-29 13:32:24 +02:00
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static_assert(GPIO_PORT_NUMOF < 3);
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volatile uword_t *in = (uint32_t *)GPIO_IN_REG;
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2022-07-27 16:35:52 +02:00
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/* return 0 for unconfigured pins, the current level at the pin otherwise */
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2024-04-29 13:32:24 +02:00
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#if GPIO_PORT_NUM > 1
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if (GPIO_PORT_NUM(port) != 0) {
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in = (uint32_t *)GPIO_IN1_REG;
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}
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#endif
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return *in;
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2022-07-27 16:35:52 +02:00
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}
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static inline uword_t gpio_ll_read_output(gpio_port_t port)
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{
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2024-04-29 13:32:24 +02:00
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static_assert(GPIO_PORT_NUMOF < 3);
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volatile uword_t *out = (uint32_t *)GPIO_OUT_REG;
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#if GPIO_PORT_NUM > 1
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if (GPIO_PORT_NUM(port) != 0) {
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out = (uint32_t *)GPIO_OUT1_REG;
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}
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#endif
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return *out;
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2022-07-27 16:35:52 +02:00
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}
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static inline void gpio_ll_set(gpio_port_t port, uword_t mask)
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{
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2024-04-29 13:32:24 +02:00
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static_assert(GPIO_PORT_NUMOF < 3);
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volatile uword_t *out_w1ts = (uint32_t *)GPIO_OUT_W1TS_REG;
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if (GPIO_PORT_NUM(port) != 0) {
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#if GPIO_PORT_NUM > 1
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out_w1ts = (uint32_t)GPIO_OUT1_W1TS;
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#endif
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}
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*out_w1ts = mask;
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2022-07-27 16:35:52 +02:00
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}
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static inline void gpio_ll_clear(gpio_port_t port, uword_t mask)
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{
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2024-04-29 13:32:24 +02:00
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static_assert(GPIO_PORT_NUMOF < 3);
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volatile uword_t *out_w1tc = (uint32_t *)GPIO_OUT_W1TC_REG;
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if (GPIO_PORT_NUM(port) != 0) {
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#if GPIO_PORT_NUM > 1
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out_w1tc = (uint32_t)GPIO_OUT1_W1TC;
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#endif
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}
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*out_w1tc = mask;
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2022-07-27 16:35:52 +02:00
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}
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static inline void gpio_ll_toggle(gpio_port_t port, uword_t mask)
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{
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2024-04-29 13:32:24 +02:00
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static_assert(GPIO_PORT_NUMOF < 3);
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volatile uword_t *out = (uint32_t *)GPIO_OUT_REG;
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#if GPIO_PORT_NUM > 1
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if (GPIO_PORT_NUM(port) != 0) {
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out = (uint32_t *)GPIO_OUT1_REG;
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}
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#endif
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unsigned irq_state = irq_disable();
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*out ^= mask;
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irq_restore(irq_state);
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2022-07-27 16:35:52 +02:00
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}
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static inline void gpio_ll_write(gpio_port_t port, uword_t value)
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{
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2024-04-29 13:32:24 +02:00
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static_assert(GPIO_PORT_NUMOF < 3);
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volatile uword_t *out = (uint32_t *)GPIO_OUT_REG;
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#if GPIO_PORT_NUM > 1
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if (GPIO_PORT_NUM(port) != 0) {
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out = (uint32_t *)GPIO_OUT1_REG;
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}
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#endif
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*out = value;
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2022-07-27 16:35:52 +02:00
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}
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static inline gpio_port_t gpio_get_port(gpio_t pin)
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{
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return GPIO_PORT(pin >> 5);
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}
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static inline uint8_t gpio_get_pin_num(gpio_t pin)
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{
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return pin & 0x1f;
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}
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static inline gpio_port_t gpio_port_pack_addr(void *addr)
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{
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return (gpio_port_t)addr;
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}
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static inline void * gpio_port_unpack_addr(gpio_port_t port)
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{
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2024-04-29 13:32:24 +02:00
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if (port <= 1) {
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return NULL;
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}
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2022-07-27 16:35:52 +02:00
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2024-04-29 13:32:24 +02:00
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return (void *)port;
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2022-07-27 16:35:52 +02:00
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}
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static inline bool is_gpio_port_num_valid(uint_fast8_t num)
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{
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return (num < GPIO_PORT_NUMOF);
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}
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#endif /* DOXYGEN */
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_LL_ARCH_H */
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