RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity

cpu/esp32: implement periph/gpio_ll

Browse Source
This commit is contained in:
Gunar Schorcht 2022-07-27 16:35:52 +02:00
parent 48d59e97a2
commit 581c2dd9be
10 changed files with 412 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
cpu/esp32/Kconfig.esp32
View File

@ -17,6 +17,7 @@ config CPU_FAM_ESP32
select HAS_ESP_BLE_ESP32
select HAS_ESP_HW_COUNTER
select HAS_ESP_WIFI_ENTERPRISE
select HAS_PERIPH_GPIO_LL
select HAS_PUF_SRAM
select PACKAGE_ESP32_SDK if TEST_KCONFIG

1
cpu/esp32/Kconfig.esp32c3
View File

@ -18,6 +18,7 @@ config CPU_FAM_ESP32C3
select HAS_ESP_BLE
select HAS_ESP_BLE_ESP32C3
select HAS_ESP_WIFI_ENTERPRISE
select HAS_PERIPH_GPIO_LL
select HAS_PUF_SRAM
select PACKAGE_ESP32_SDK if TEST_KCONFIG

1
cpu/esp32/Kconfig.esp32s2
View File

@ -13,6 +13,7 @@ config CPU_FAM_ESP32S2
select HAS_CPU_ESP32
select HAS_ESP_HW_COUNTER
select HAS_ESP_WIFI_ENTERPRISE
select HAS_PERIPH_GPIO_LL
select HAS_PUF_SRAM
select PACKAGE_ESP32_SDK if TEST_KCONFIG

1
cpu/esp32/Kconfig.esp32s3
View File

@ -19,6 +19,7 @@ config CPU_FAM_ESP32S3
select HAS_ESP_BLE_ESP32C3
select HAS_ESP_HW_COUNTER
select HAS_ESP_WIFI_ENTERPRISE
select HAS_PERIPH_GPIO_LL
select HAS_PUF_SRAM
select PACKAGE_ESP32_SDK if TEST_KCONFIG

1
cpu/esp32/Makefile.features
View File

@ -17,6 +17,7 @@ include $(RIOTCPU)/esp_common/Makefile.features
FEATURES_PROVIDED += arch_esp32
FEATURES_PROVIDED += esp_wifi_enterprise
FEATURES_PROVIDED += periph_gpio_ll
FEATURES_PROVIDED += puf_sram
ifeq (xtensa,$(CPU_ARCH))

2
cpu/esp32/include/gpio_arch.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2018 Gunar Schorcht
* Copyright (C) 2021 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level

133
cpu/esp32/include/gpio_ll_arch.h Normal file
View File

@ -0,0 +1,133 @@
/*
* Copyright (C) 2021 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_esp32
* @ingroup drivers_periph_gpio_ll
* @{
*
* @file
* @brief CPU specific part of the Peripheral GPIO Low-Level API
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @}
*/
#ifndef GPIO_LL_ARCH_H
#define GPIO_LL_ARCH_H
#include "gpio_arch.h"
#include "soc/soc.h"
#include "soc/gpio_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifndef DOXYGEN /* hide implementation specific details from Doxygen */
#define GPIO_PORT(num) ((gpio_port_t)(&_esp32_ports[num]))
#define GPIO_PORT_NUM(port) (((_esp32_port_t*)port == _esp32_ports) ? 0 : 1)
/* GPIO port descriptor type */
typedef struct {
volatile uint32_t *out; /* address of GPIO_OUT/GPIO_OUT1 */
volatile uint32_t *out_w1ts; /* address of GPIO_OUT_W1TS/GPIO_OUT1_W1TC */
volatile uint32_t *out_w1tc; /* address of GPIO_OUT_W1TC/GPIO_OUT1_W1TC */
volatile uint32_t *in; /* address of GPIO_IN/GPIO_IN1 */
volatile uint32_t *enable; /* address of GPIO_ENABLE/GPIO_ENABLE1 */
volatile uint32_t *enable_w1ts; /* address of GPIO_ENABLE_W1TS/GPIO_ENABLE1_W1TS */
volatile uint32_t *enable_w1tc; /* address of GPIO_ENABLE_W1TC/GPIO_ENABLE1_W1TC */
volatile uint32_t *status_w1tc; /* address of GPIO_STATUS_W1TC/GPIO_STATUS1_W1TC */
} _esp32_port_t;
/* GPIO port table */
extern const _esp32_port_t _esp32_ports[];
static inline uword_t gpio_ll_read(gpio_port_t port)
{
/* return 0 for unconfigured pins, the current level at the pin otherwise */
const _esp32_port_t *p = (_esp32_port_t *)port;
return *p->in;
}
static inline uword_t gpio_ll_read_output(gpio_port_t port)
{
/* return output register bits */
const _esp32_port_t *p = (_esp32_port_t *)port;
return *p->out;
}
static inline void gpio_ll_set(gpio_port_t port, uword_t mask)
{
/* set output register bits for configured pins in the mask */
const _esp32_port_t *p = (_esp32_port_t *)port;
*p->out_w1ts = mask;
}
static inline void gpio_ll_clear(gpio_port_t port, uword_t mask)
{
/* clear output register bits for configured pins in the mask */
const _esp32_port_t *p = (_esp32_port_t *)port;
*p->out_w1tc = mask;
}
static inline void gpio_ll_toggle(gpio_port_t port, uword_t mask)
{
/* toggle output register bits for configured pins in the mask */
const _esp32_port_t *p = (_esp32_port_t *)port;
*p->out ^= mask;
}
static inline void gpio_ll_write(gpio_port_t port, uword_t value)
{
/* write output register bits for configured pins in the mask */
const _esp32_port_t *p = (_esp32_port_t *)port;
*p->out = value;
}
static inline gpio_port_t gpio_get_port(gpio_t pin)
{
return GPIO_PORT(pin >> 5);
}
static inline uint8_t gpio_get_pin_num(gpio_t pin)
{
return pin & 0x1f;
}
static inline gpio_port_t gpio_port_pack_addr(void *addr)
{
return (gpio_port_t)addr;
}
static inline void * gpio_port_unpack_addr(gpio_port_t port)
{
const _esp32_port_t *p = (_esp32_port_t *)port;
/* return NULL if port is one of the port descriptors in GPIO port table */
#if GPIO_PORT_NUMOF > 1
return ((p == &_esp32_ports[0]) ||
(p == &_esp32_ports[1])) ? NULL : (void *)port;
#else
return (p == _esp32_ports) ? NULL : (void *)port;
#endif
}
static inline bool is_gpio_port_num_valid(uint_fast8_t num)
{
return (num < GPIO_PORT_NUMOF);
}
#endif /* DOXYGEN */
#ifdef __cplusplus
}
#endif
#endif /* GPIO_LL_ARCH_H */

70
cpu/esp32/include/periph_cpu.h
View File

@ -88,7 +88,7 @@ typedef unsigned int gpio_t;
* @brief Define a CPU specific GPIO pin generator macro
* @{
*/
#define GPIO_PIN(x, y) ((x & 0) | y)
#define GPIO_PIN(x, y) ((x << 5) | y)
/** @} */
/**
@ -141,6 +141,74 @@ typedef enum {
} gpio_mode_t;
/** @} */
/* BEGIN: GPIO LL overwrites */
#if SOC_GPIO_PIN_COUNT > 32
#define GPIO_PORT_NUMOF 2
#define GPIO_PORT_0 GPIO_PORT(0)
#define GPIO_PORT_1 GPIO_PORT(1)
#define GPIO_PORT_0_PIN_NUMOF (32)
#define GPIO_PORT_1_PIN_NUMOF (SOC_GPIO_PIN_COUNT - 32)
#define GPIO_PORT_PIN_NUMOF(p) ((p == GPIO_PORT_0) ? GPIO_PORT_0_PIN_NUMOF \
: GPIO_PORT_1_PIN_NUMOF)
#else
#define GPIO_PORT_NUMOF 1
#define GPIO_PORT_0 GPIO_PORT(0)
#define GPIO_PORT_0_PIN_NUMOF (SOC_GPIO_PIN_COUNT)
#define GPIO_PORT_PIN_NUMOF(p) ((p == GPIO_PORT_0) ? GPIO_PORT_0_PIN_NUMOF : 0)
#endif
#define HAVE_GPIO_PORT_T
typedef uintptr_t gpio_port_t;
#define HAVE_GPIO_SLEW_T
typedef enum {
GPIO_SLEW_SLOWEST = 0,
GPIO_SLEW_SLOW = 0,
GPIO_SLEW_FAST = 0,
GPIO_SLEW_FASTEST = 0,
} gpio_slew_t;
#define HAVE_GPIO_PULL_STRENGTH_T
typedef enum {
GPIO_PULL_WEAKEST = 0,
GPIO_PULL_WEAK = 0,
GPIO_PULL_STRONG = 0,
GPIO_PULL_STRONGEST = 0
} gpio_pull_strength_t;
#define HAVE_GPIO_PULL_T
typedef enum {
GPIO_FLOATING = 0,
GPIO_PULL_UP = 1,
GPIO_PULL_DOWN = 2,
GPIO_PULL_KEEP = 0xff /*< not supported */
} gpio_pull_t;
/**
* @brief Current an output pin can drive in active and sleep modes
*/
#define HAVE_GPIO_DRIVE_STRENGTH_T
typedef enum {
GPIO_DRIVE_WEAKEST = 0, /**< 5 mA */
GPIO_DRIVE_WEAK = 1, /**< 10 mA */
GPIO_DRIVE_STRONG = 2, /**< 20 mA (default) */
GPIO_DRIVE_STRONGEST = 3, /**< 30 mA */
} gpio_drive_strength_t;
/*
* @brief Map former enumeration values the new enumeration values for compatibility.
*/
#define GPIO_DRIVE_5 GPIO_DRIVE_WEAKEST /**< 5 mA */
#define GPIO_DRIVE_10 GPIO_DRIVE_WEAK /**< 10 mA */
#define GPIO_DRIVE_20 GPIO_DRIVE_STRONG /**< 20 mA (default) */
#define GPIO_DRIVE_30 GPIO_DRIVE_STRONGEST /**< 30 mA */
/* END: GPIO LL overwrites */
#endif /* ndef DOXYGEN */
/** @} */

44
cpu/esp32/periph/gpio.c
View File

@ -23,12 +23,15 @@
#include "log.h"
#include "periph/gpio.h" /* RIOT gpio.h */
#if IS_USED(MODULE_GPIO_LL)
#include "periph/gpio_ll_arch.h"
#endif
#include "esp/common_macros.h"
#include "esp_intr_alloc.h"
#include "hal/gpio_hal.h"
#include "hal/gpio_types.h"
#include "hal/rtc_io_types.h"
#include "esp/common_macros.h"
#include "esp_intr_alloc.h"
#include "rom/ets_sys.h"
#include "soc/gpio_reg.h"
#include "soc/gpio_sig_map.h"
@ -97,8 +100,8 @@ const char* _gpio_pin_usage_str[] =
#ifdef ESP_PM_WUP_PINS
/* for saving the pullup/pulldown settings of wakeup pins in deep sleep mode */
static bool _gpio_pin_pu[GPIO_PIN_NUMOF] = { };
static bool _gpio_pin_pd[GPIO_PIN_NUMOF] = { };
bool _gpio_pin_pu[GPIO_PIN_NUMOF] = { };
bool _gpio_pin_pd[GPIO_PIN_NUMOF] = { };
#endif
#if SOC_GPIO_PIN_COUNT > 32
@ -197,11 +200,6 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
gpio_config_t cfg = { };
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
/* if we come from deep sleep, the GPIO is configured as RTC IO */
esp_idf_rtc_gpio_deinit(pin);
#endif
cfg.pin_bit_mask = (1ULL << pin);
switch (mode) {
@ -212,17 +210,17 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
break;
case GPIO_IN_OD:
case GPIO_IN_OD_PU:
cfg.mode = (GPIO_MODE_DEF_INPUT) | (GPIO_MODE_DEF_OUTPUT) | (GPIO_MODE_DEF_OD);
cfg.mode = GPIO_MODE_DEF_INPUT | GPIO_MODE_DEF_OUTPUT | GPIO_MODE_DEF_OD;
break;
case GPIO_IN_OUT:
cfg.mode = (GPIO_MODE_DEF_INPUT) | (GPIO_MODE_DEF_OUTPUT);
cfg.mode = GPIO_MODE_DEF_INPUT | GPIO_MODE_DEF_OUTPUT;
break;
case GPIO_OUT:
cfg.mode = GPIO_MODE_DEF_OUTPUT;
break;
case GPIO_OD:
case GPIO_OD_PU:
cfg.mode = (GPIO_MODE_DEF_OUTPUT) | (GPIO_MODE_DEF_OD);
cfg.mode = GPIO_MODE_DEF_OUTPUT | GPIO_MODE_DEF_OD;
break;
}
@ -247,9 +245,8 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
#if MODULE_PERIPH_GPIO_IRQ
/* interrupt enabled state is required for sleep modes */
static bool gpio_int_enabled_table[GPIO_PIN_NUMOF] = { };
static bool _isr_installed = false;
bool gpio_int_enabled_table[GPIO_PIN_NUMOF] = { };
bool gpio_isr_service_installed = false;
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
@ -284,16 +281,19 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
break;
}
/* install GPIO ISR of ESP-IDF if not yet done */
if (!gpio_isr_service_installed &&
esp_idf_gpio_install_isr_service(ESP_INTR_FLAG_LEVEL1) != ESP_OK) {
return -1;
}
gpio_isr_service_installed = true;
/* set the interrupt type for the pin */
if (esp_idf_gpio_set_intr_type(pin, type) != ESP_OK) {
return -1;
}
if (!_isr_installed &&
esp_idf_gpio_install_isr_service(ESP_INTR_FLAG_LEVEL1) != ESP_OK) {
return -1;
}
_isr_installed = true;
/* unmask and clear pending interrupts for the pin */
if (esp_idf_gpio_isr_handler_add(pin, cb, arg) != ESP_OK) {
return -1;
}
@ -328,7 +328,7 @@ void gpio_irq_disable(gpio_t pin)
#if IS_USED(MODULE_ESP_IDF_GPIO_HAL)
static gpio_hal_context_t _gpio_hal_ctx = {
.dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
.dev = GPIO_HAL_GET_HW(0)
};
/*

182
cpu/esp32/periph/gpio_ll.c Normal file
View File

@ -0,0 +1,182 @@
/*
* Copyright (C) 2021 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_esp32
* @ingroup drivers_periph_gpio_ll
* @{
*
* @file
* @brief Peripheral GPIO Low-Level API implementation for the ESP32
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @}
*/
#define ENABLE_DEBUG 0
#include "debug.h"
#include <assert.h>
#include <errno.h>
#include <stdbool.h>
#include <string.h>
#include "log.h"
#include "irq.h"
#include "periph/gpio_ll.h"
#include "esp/common_macros.h"
#include "hal/gpio_hal.h"
#include "hal/gpio_types.h"
#include "gpio_ll_arch.h"
#include "soc/gpio_reg.h"
#include "esp_idf_api/gpio.h"
/* variables that have to be used together with periph/gpio */
#ifdef ESP_PM_WUP_PINS
extern bool _gpio_pin_pu[GPIO_PIN_NUMOF];
extern bool _gpio_pin_pd[GPIO_PIN_NUMOF];
#endif
static gpio_conf_t _gpio_conf[GPIO_PIN_NUMOF] = { };
const _esp32_port_t _esp32_ports[GPIO_PORT_NUMOF] = {
{
.out = (uint32_t *)GPIO_OUT_REG,
.out_w1ts = (uint32_t *)GPIO_OUT_W1TS_REG,
.out_w1tc = (uint32_t *)GPIO_OUT_W1TC_REG,
.in = (uint32_t *)GPIO_IN_REG,
.enable = (uint32_t *)GPIO_ENABLE_REG,
.enable_w1ts = (uint32_t *)GPIO_ENABLE_W1TS_REG,
.enable_w1tc = (uint32_t *)GPIO_ENABLE_W1TC_REG,
.status_w1tc = (uint32_t *)GPIO_STATUS_W1TC_REG,
},
#if GPIO_PORT_NUMOF > 1
{
.out = (uint32_t *)GPIO_OUT1_REG,
.out_w1ts = (uint32_t *)GPIO_OUT1_W1TS_REG,
.out_w1tc = (uint32_t *)GPIO_OUT1_W1TC_REG,
.in = (uint32_t *)GPIO_IN1_REG,
.enable = (uint32_t *)GPIO_ENABLE1_REG,
.enable_w1ts = (uint32_t *)GPIO_ENABLE1_W1TS_REG,
.enable_w1tc = (uint32_t *)GPIO_ENABLE1_W1TC_REG,
.status_w1tc = (uint32_t *)GPIO_STATUS1_W1TC_REG,
}
#endif
};
int gpio_ll_init(gpio_port_t port, uint8_t pin, const gpio_conf_t *conf)
{
assert(port);
assert(conf);
assert(GPIO_PORT_NUM(port) < GPIO_PORT_NUMOF);
assert(pin < GPIO_PORT_PIN_NUMOF(port));
gpio_t gpio = GPIO_PIN(GPIO_PORT_NUM(port), pin);
gpio_config_t cfg = {
.pin_bit_mask = (1ULL << gpio),
.intr_type = GPIO_INTR_DISABLE,
.pull_up_en = false,
.pull_down_en = false,
};
switch (conf->state) {
case GPIO_OUTPUT_PUSH_PULL:
cfg.mode = GPIO_MODE_DEF_OUTPUT;
break;
case GPIO_OUTPUT_OPEN_DRAIN:
cfg.mode = GPIO_MODE_DEF_OUTPUT | GPIO_MODE_DEF_OD;
break;
case GPIO_INPUT:
cfg.mode = GPIO_MODE_DEF_INPUT;
break;
case GPIO_DISCONNECT:
cfg.mode = GPIO_MODE_DEF_DISABLE;
break;
default:
return -ENOTSUP;
}
switch (conf->pull) {
case GPIO_FLOATING:
break;
case GPIO_PULL_UP:
cfg.pull_up_en = true;
break;
case GPIO_PULL_DOWN:
cfg.pull_down_en = true;
break;
default:
return -ENOTSUP;
}
/* Some ESP32x GPIOs may not be available at all */
if (cfg.pin_bit_mask & ~SOC_GPIO_VALID_GPIO_MASK) {
return -ENOTSUP;
}
/* Some ESP32x GPIOs may have limited features (input only and no pull-up/-down) */
if ((cfg.pin_bit_mask & ~SOC_GPIO_VALID_OUTPUT_GPIO_MASK) &&
((cfg.mode & GPIO_MODE_DEF_OUTPUT) || cfg.pull_up_en || cfg.pull_down_en)) {
return -ENOTSUP;
}
#ifdef ESP_PM_WUP_PINS
/* for saving the pullup/pulldown settings of wakeup pins in deep sleep mode */
_gpio_pin_pu[pin] = cfg.pull_up_en;
_gpio_pin_pd[pin] = cfg.pull_down_en;
#endif
if (conf->state == GPIO_DISCONNECT) {
/* reset the pin to disconnects any other peripheral output configured
via GPIO Matrix, the pin is reconfigured according to given conf */
esp_idf_gpio_reset_pin(gpio);
}
/* since we can't read back the configuration, we have to save it */
_gpio_conf[gpio] = *conf;
_gpio_conf[gpio].schmitt_trigger = false;
if (esp_idf_gpio_config(&cfg) != ESP_OK) {
return -ENOTSUP;
}
/* if output pin, try to set drive strength */
if ((cfg.pin_bit_mask & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) &&
(esp_idf_gpio_set_drive_capability(gpio,
conf->drive_strength) != ESP_OK)) {
return -ENOTSUP;
}
if (conf->initial_value) {
gpio_ll_set(port, 1UL << pin);
}
else {
gpio_ll_clear(port, 1UL << pin);
}
return 0;
}
void gpio_ll_query_conf(gpio_conf_t *dest, gpio_port_t port, uint8_t pin)
{
assert(dest);
unsigned state = irq_disable();
*dest = _gpio_conf[GPIO_PIN(GPIO_PORT_NUM(port), pin)];
if (dest->state == GPIO_INPUT) {
dest->initial_value = (gpio_ll_read(port) >> pin) & 1UL;
}
else {
dest->initial_value = (gpio_ll_read_output(port) >> pin) & 1UL;
}
irq_restore(state);
}