2014-07-31 19:59:02 +02:00
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/*
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* Copyright (C) 2013 Milan Babel <babel@inf.fu-berlin.de>
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2017-11-16 15:31:45 +01:00
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* 2017 Freie Universität Berlin
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2014-07-31 19:59:02 +02:00
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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2013-05-25 12:34:18 +02:00
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2017-11-30 23:37:28 +01:00
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/**
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* @ingroup boards_common_wsn430
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* @{
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*
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* @file
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* @brief Board initialization for WSN430
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*
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* @author Milan Babel <babel@inf.fu-berlin.de>
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2017-11-16 15:31:45 +01:00
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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2017-11-30 23:37:28 +01:00
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*
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* @}
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*/
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2013-05-25 12:34:18 +02:00
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#include "cpu.h"
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2015-09-02 17:06:12 +02:00
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#include "irq.h"
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2017-11-16 15:31:45 +01:00
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#include "assert.h"
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2018-07-05 14:09:08 +02:00
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#include "stdio_uart.h"
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2017-11-16 15:31:45 +01:00
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#include "periph_conf.h"
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2013-05-25 12:34:18 +02:00
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2017-11-16 15:31:45 +01:00
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enum {
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MCLK_2MHZ_SCLK_1MHZ = (SELM_2 | DIVM_2 | SELS | DIVS_3),
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MCLK_4MHZ_SCLK_1MHZ = (SELM_2 | DIVM_1 | SELS | DIVS_3),
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MCLK_8MHZ_SCLK_1MHZ = (SELM_2 | SELS | DIVS_3),
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MCLK_8MHZ_SCLK_8MHZ = (SELM_2 | SELS),
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};
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2013-05-25 12:34:18 +02:00
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static void msb_ports_init(void)
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{
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2017-11-16 15:31:45 +01:00
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/* Port 1: GDO, Flash, BSL TX */
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P1SEL = 0x02; /* Port1 Select: 00000010 = 0x02 */
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P1OUT = 0x00; /* Port1 Output: 00000000 = 0x00 */
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P1DIR = 0x87; /* Port1 Direction: 10000111 = 0x87 */
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2013-05-25 12:34:18 +02:00
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2017-11-16 15:31:45 +01:00
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/* Port 2: GPIO, BSL RX, 1wire */
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P2SEL = 0x04; /* Port2 Select: 00000100 = 0x04 */
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P2OUT = 0x00; /* Port2 Output: 00000000 = 0x00 */
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P2DIR = 0xFF; /* Port2 Direction: 11111111 = 0xFF */
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2013-05-25 12:34:18 +02:00
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2017-11-16 15:31:45 +01:00
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/* Port 3: UART */
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P3SEL = 0xFE; /* Port3 Select: 11111110 = 0xFE */
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P3OUT = 0x00; /* Port3 Output: 00000000 = 0x00 */
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P3DIR = 0xFF; /* Port3 Direction: 11111111 = 0xFF */
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2013-05-25 12:34:18 +02:00
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2017-11-16 15:31:45 +01:00
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/* Port 4: CS */
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P4SEL = 0x00; /* Port4 Select: 00000000 = 0x00 */
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P4OUT = 0x14; /* Port4 Output: 00010100 = 0x14 */
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P4DIR = 0xFF; /* Port4 Direction: 11111111 = 0xFF */
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2013-05-25 12:34:18 +02:00
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2017-11-16 15:31:45 +01:00
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/* Port 5: SPI, LED */
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P5SEL = 0x0E; /* Port5 Select: 00001110 = 0x0E */
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P5OUT = 0x70; /* Port5 Output: 01110000 = 0x70 */
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P5DIR = 0x70; /* Port5 Direction: 01110000 = 0x70 */
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2013-05-25 12:34:18 +02:00
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2017-11-16 15:31:45 +01:00
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P6SEL = 0xFF; /* Port6 Select: 11111111 = 0xFF */
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P6OUT = 0x00; /* Port6 Output: 00000000 = 0x00 */
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P6DIR = 0xFF; /* Port6 Direction: 11111000 = 0xF8 */
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2013-05-25 12:34:18 +02:00
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}
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2017-11-16 15:31:45 +01:00
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static void msp430_init_cpuclk(uint8_t speed)
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2013-05-25 12:34:18 +02:00
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{
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2017-11-16 15:31:45 +01:00
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/* stop watchdog */
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WDTCTL = WDTPW + WDTHOLD;
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BCSCTL1 = RSEL2;
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/* wait for XTAL to stabilize */
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do {
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/* clear oscillator fault flag */
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IFG1 &= ~OFIFG;
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/* time for flag to set */
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for (uint16_t i = 0xFF; i > 0; i--) {}
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} while ((IFG1 & OFIFG) != 0);
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/* apply clock config */
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BCSCTL2 = speed;
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2013-05-25 12:34:18 +02:00
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}
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2014-05-07 12:36:32 +02:00
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void board_init(void)
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{
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2013-05-25 12:34:18 +02:00
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msp430_cpu_init();
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msb_ports_init();
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2014-02-11 18:15:43 +01:00
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2017-11-16 15:31:45 +01:00
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/* initialize CPU clock */
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unsigned state = irq_disable();
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msp430_init_cpuclk(CLOCK_MODE);
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irq_restore(state);
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2015-08-28 19:05:53 +02:00
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2016-03-09 19:39:34 +01:00
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/* initialize STDIO over UART */
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2018-07-05 14:09:08 +02:00
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stdio_init();
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2013-05-25 12:34:18 +02:00
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}
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