2020-08-24 08:26:44 +02:00
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# Copyright (c) 2020 Inria
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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2020-12-31 17:35:05 +01:00
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config CLOCK_HAS_NO_MCO_PRE
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bool
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help
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Indicates that the CPU has no MCO prescaler
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2020-08-24 08:26:44 +02:00
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choice
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bool "Clock source selection"
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default USE_CLOCK_PLL
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config USE_CLOCK_PLL
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bool "PLL"
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config USE_CLOCK_HSE
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bool "Direct High frequency external oscillator (HSE)"
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depends on BOARD_HAS_HSE
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config USE_CLOCK_HSI
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bool "Direct High frequency internal oscillator (HSI16)"
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endchoice
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2022-10-26 11:55:43 +02:00
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config CLOCK_HSE
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int
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2020-08-26 18:57:03 +02:00
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depends on BOARD_HAS_HSE
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2022-10-26 11:55:43 +02:00
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default 24000000 if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_MP1
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default 8000000
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2020-08-26 18:57:03 +02:00
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config CUSTOM_PLL_PARAMS
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bool "Configure PLL parameters"
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depends on USE_CLOCK_PLL
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2020-08-24 08:26:44 +02:00
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choice
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bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
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2022-01-10 13:10:28 +01:00
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default CLOCK_APB1_DIV_4 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_U5 || CPU_FAM_WB || CPU_FAM_WL
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2022-01-14 14:15:32 +01:00
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default CLOCK_APB1_DIV_2 if CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_F4 || CPU_FAM_MP1
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2020-08-24 08:26:44 +02:00
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default CLOCK_APB1_DIV_1
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config CLOCK_APB1_DIV_1
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bool "Divide HCLK by 1"
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config CLOCK_APB1_DIV_2
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bool "Divide HCLK by 2"
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config CLOCK_APB1_DIV_4
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bool "Divide HCLK by 4"
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config CLOCK_APB1_DIV_8
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bool "Divide HCLK by 8"
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config CLOCK_APB1_DIV_16
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bool "Divide HCLK by 16"
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endchoice
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config CLOCK_APB1_DIV
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int
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default 1 if CLOCK_APB1_DIV_1
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default 2 if CLOCK_APB1_DIV_2
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default 4 if CLOCK_APB1_DIV_4
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default 8 if CLOCK_APB1_DIV_8
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default 16 if CLOCK_APB1_DIV_16
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choice
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2020-08-28 20:19:37 +02:00
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bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
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2020-10-31 17:17:18 +01:00
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depends on !CPU_FAM_G0 && !CPU_FAM_F0
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2022-01-10 13:10:28 +01:00
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default CLOCK_APB2_DIV_2 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_U5 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1
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2020-08-24 08:26:44 +02:00
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default CLOCK_APB2_DIV_1
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config CLOCK_APB2_DIV_1
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bool "Divide HCLK by 1"
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config CLOCK_APB2_DIV_2
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bool "Divide HCLK by 2"
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config CLOCK_APB2_DIV_4
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bool "Divide HCLK by 4"
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config CLOCK_APB2_DIV_8
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bool "Divide HCLK by 8"
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config CLOCK_APB2_DIV_16
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bool "Divide HCLK by 16"
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endchoice
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config CLOCK_APB2_DIV
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int
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default 1 if CLOCK_APB2_DIV_1
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default 2 if CLOCK_APB2_DIV_2
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default 4 if CLOCK_APB2_DIV_4
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default 8 if CLOCK_APB2_DIV_8
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default 16 if CLOCK_APB2_DIV_16
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