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https://github.com/RIOT-OS/RIOT.git
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cpu/stm32/kconfig: rework clock tree
This splits up the clock configs. It allows CPU_FAM based file sourcing and also common CPU_FAMs. The dependancies are also included in wildcards would be used for the CPU_FAM macro. This should be much more readable. This also takes into account the HSE speeds in order to match the make/header resolution. Some hidden symbols were added to make sorting many CPU_SERIES dependencies easier.
This commit is contained in:
MrKevinWeiss
parent
ba4843b5f4
commit
28aed3cb97
@ -19,6 +19,8 @@ config CPU_STM32
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# This CPU requires periph_rtc when periph_rtc_mem
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select MODULE_PERIPH_RTC if MODULE_PERIPH_RTC_MEM && HAS_PERIPH_RTC
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menu "STM32 configuration"
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# Common CPU symbol
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config CPU
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default "stm32" if CPU_STM32
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@ -39,10 +41,18 @@ config MODULE_BOOTLOADER_STM32
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depends on HAS_BOOTLOADER_STM32
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depends on TEST_KCONFIG
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orsource "kconfigs/Kconfig.clk"
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orsource "kconfigs/*/Kconfig"
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orsource "kconfigs/*/Kconfig.lines"
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orsource "kconfigs/*/Kconfig.models"
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menu "STM32 clock configuration"
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depends on CPU_STM32
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rsource "kconfigs/Kconfig.clk"
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rsource "kconfigs/$(CPU_FAM)/Kconfig.clk"
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endmenu
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rsource "kconfigs/$(CPU_FAM)/Kconfig"
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rsource "kconfigs/$(CPU_FAM)/Kconfig.lines"
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rsource "kconfigs/$(CPU_FAM)/Kconfig.models"
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choice
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prompt "ReaDout Protection level"
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@ -72,4 +82,6 @@ rsource "vectors/Kconfig"
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endif # TEST_KCONFIG
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endmenu
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source "$(RIOTCPU)/cortexm_common/Kconfig"
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@ -10,8 +10,6 @@ config CLOCK_HAS_NO_MCO_PRE
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help
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Indicates that the CPU has no MCO prescaler
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menu "STM32 clock configuration"
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depends on CPU_STM32
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choice
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bool "Clock source selection"
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@ -20,10 +18,6 @@ default USE_CLOCK_PLL
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config USE_CLOCK_PLL
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bool "PLL"
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config USE_CLOCK_MSI
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bool "Use direct multi-speed frequency internal oscillator (MSI)"
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depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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config USE_CLOCK_HSE
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bool "Direct High frequency external oscillator (HSE)"
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depends on BOARD_HAS_HSE
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@ -33,345 +27,16 @@ config USE_CLOCK_HSI
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endchoice
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if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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choice
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bool "Source clock for PLL" if USE_CLOCK_PLL
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default CLOCK_PLL_SRC_HSE if BOARD_HAS_HSE
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default CLOCK_PLL_SRC_MSI
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config CLOCK_PLL_SRC_MSI
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bool "Use MSI source clock"
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config CLOCK_PLL_SRC_HSE
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bool "Use HSE source clock"
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config CLOCK_HSE
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int
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depends on BOARD_HAS_HSE
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config CLOCK_PLL_SRC_HSI
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bool "Use HSI16 source clock"
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endchoice
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endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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default 24000000 if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_MP1
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default 8000000
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config CUSTOM_PLL_PARAMS
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bool "Configure PLL parameters"
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depends on USE_CLOCK_PLL
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if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_MP1
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config CLOCK_PLL_M
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int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
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default 4 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
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default 1 if CPU_FAM_G0
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default 6 if CPU_FAM_G4 && BOARD_HAS_HSE
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default 4 if CPU_FAM_G4
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default 6 if (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL) && CLOCK_PLL_SRC_MSI
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default 4 if (CPU_FAM_WB || CPU_FAM_WL) && CLOCK_PLL_SRC_HSE
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default 2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1
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range 1 8 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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range 1 16 if CPU_FAM_G4
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config CLOCK_PLL_N
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int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
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default 120 if BOARD_HAS_HSE && CPU_FAM_F2
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default 60 if CPU_FAM_F2
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default 168 if CPU_FAM_F4 && CLOCK_MAX_84MHZ && BOARD_HAS_HSE
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default 84 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
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default 96 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK)
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default 48 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK)
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default 100 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE
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default 50 if CPU_FAM_F4 && CLOCK_MAX_100MHZ
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default 168 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK)
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default 84 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK)
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default 180 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE
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default 90 if CPU_FAM_F4 && CLOCK_MAX_180MHZ
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default 216 if CPU_FAM_F7 && BOARD_HAS_HSE
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default 108 if CPU_FAM_F7
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default 12 if CPU_FAM_WL
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default 16 if CPU_FAM_WB
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default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX
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default 27 if CPU_FAM_L5
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default 20 if CPU_FAM_G0 || CPU_FAM_L4
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default 85 if CPU_FAM_G4
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default 52 if CPU_FAM_MP1 && BOARD_HAS_HSE
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default 78 if CPU_FAM_MP1
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range 8 86 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5
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range 50 432 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
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range 8 127 if CPU_FAM_G4
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range 6 127 if CPU_FAM_WB || CPU_FAM_WL
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range 4 512 if CPU_FAM_MP1
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if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1
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choice
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bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS
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default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
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default PLL_P_DIV_2
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config PLL_P_DIV_2
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bool "Divide by 2"
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config PLL_P_DIV_4
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bool "Divide by 4"
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config PLL_P_DIV_6
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bool "Divide by 6"
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config PLL_P_DIV_8
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bool "Divide by 8"
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endchoice
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config CLOCK_PLL_P
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int
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default 3 if CPU_FAM_MP1
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default 2 if PLL_P_DIV_2
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default 4 if PLL_P_DIV_4
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default 6 if PLL_P_DIV_6
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default 8 if PLL_P_DIV_8
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config CLOCK_PLL_Q
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int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS
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default 5 if CPU_FAM_F2
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default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
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default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ
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default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK)
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default 9 if CPU_FAM_F7
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default 13 if CPU_FAM_MP1
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default 8
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range 2 15
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endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1
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if CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1
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config CLOCK_PLL_R
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int "Q: VCO division factor" if CUSTOM_PLL_PARAMS
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default 2 if CPU_FAM_WB || CPU_FAM_WL
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default 3 if CPU_FAM_MP1
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default 6 if BOARD_HAS_HSE
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default 5
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range 2 8
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endif # CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1
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if CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
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choice
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bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if CUSTOM_PLL_PARAMS
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default PLL_R_DIV_2
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config PLL_R_DIV_2
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bool "Divide by 2"
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config PLL_R_DIV_4
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bool "Divide by 4"
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config PLL_R_DIV_6
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bool "Divide by 6"
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config PLL_R_DIV_8
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bool "Divide by 8"
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endchoice
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config CLOCK_PLL_R
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int
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default 2 if PLL_R_DIV_2
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default 4 if PLL_R_DIV_4
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default 6 if PLL_R_DIV_6
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default 8 if PLL_R_DIV_8
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endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
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endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1
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if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3
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config CLOCK_PLL_PREDIV
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int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6 && !CPU_LINE_STM32F303X8
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default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 || CPU_LINE_STM32F303X8 || CPU_LINE_STM32F303XC
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default 1
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range 1 16
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config CLOCK_PLL_MUL
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int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS
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default 16 if CPU_LINE_STM32F303X8
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default 12 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6
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default 9 if CPU_FAM_F1 || CPU_FAM_F3
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default 6 if CPU_FAM_F0
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range 2 16
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endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3
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if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_PLL_DIV
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int "Main PLL division factor" if CUSTOM_PLL_PARAMS
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default 2
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range 2 4
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choice
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bool "Main PLL multiply factor" if CUSTOM_PLL_PARAMS
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default PLL_MUL_4
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config PLL_MUL_3
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bool "Multiply by 3"
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config PLL_MUL_4
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bool "Multiply by 4"
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config PLL_MUL_6
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bool "Multiply by 6"
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config PLL_MUL_8
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bool "Multiply by 8"
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config PLL_MUL_12
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bool "Multiply by 12"
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config PLL_MUL_16
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bool "Multiply by 16"
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config PLL_MUL_24
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bool "Multiply by 24"
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config PLL_MUL_32
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bool "Multiply by 32"
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config PLL_MUL_48
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bool "Multiply by 48"
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endchoice
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config CLOCK_PLL_MUL
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int
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default 3 if PLL_MUL_3
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default 4 if PLL_MUL_4
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default 6 if PLL_MUL_6
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default 8 if PLL_MUL_8
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default 12 if PLL_MUL_12
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default 16 if PLL_MUL_16
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default 24 if PLL_MUL_24
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default 32 if PLL_MUL_32
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default 48 if PLL_MUL_48
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endif # CPU_FAM_L0 || CPU_FAM_L1
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if CPU_FAM_G0
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choice
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bool "HSISYS division factor" if USE_CLOCK_HSI
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default CLOCK_HSISYS_DIV_1
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config CLOCK_HSISYS_DIV_1
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bool "Divide HSISYS by 1"
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config CLOCK_HSISYS_DIV_2
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bool "Divide HSISYS by 2"
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config CLOCK_HSISYS_DIV_4
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bool "Divide HSISYS by 4"
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config CLOCK_HSISYS_DIV_8
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bool "Divide HSISYS by 8"
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config CLOCK_HSISYS_DIV_16
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bool "Divide HSISYS by 16"
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config CLOCK_HSISYS_DIV_32
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bool "Divide HSISYS by 32"
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config CLOCK_HSISYS_DIV_64
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bool "Divide HSISYS by 64"
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config CLOCK_HSISYS_DIV_128
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bool "Divide HSISYS by 128"
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endchoice
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config CLOCK_HSISYS_DIV
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int
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default 1 if CLOCK_HSISYS_DIV_1
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default 2 if CLOCK_HSISYS_DIV_2
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default 4 if CLOCK_HSISYS_DIV_4
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default 8 if CLOCK_HSISYS_DIV_8
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default 16 if CLOCK_HSISYS_DIV_16
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default 32 if CLOCK_HSISYS_DIV_32
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default 64 if CLOCK_HSISYS_DIV_64
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default 128 if CLOCK_HSISYS_DIV_128
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endif # CPU_FAM_G0
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if CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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choice
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bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI)
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default CLOCK_MSI_48MHZ if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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default CLOCK_MSI_4MHZ
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config CLOCK_MSI_65KHZ
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bool "65.536kHz" if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_MSI_100KHZ
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bool "100kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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config CLOCK_MSI_130KHZ
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bool "131.072kHz" if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_MSI_200KHZ
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bool "200kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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config CLOCK_MSI_260KHZ
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bool "262.144kHz" if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_MSI_400KHZ
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bool "400kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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config CLOCK_MSI_520KHZ
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bool "524.288kHz" if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_MSI_800KHZ
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bool "800kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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config CLOCK_MSI_1MHZ
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bool
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prompt "1MHz"
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config CLOCK_MSI_2MHZ
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bool
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prompt "2MHz"
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config CLOCK_MSI_4MHZ
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bool
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prompt "4MHz"
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config CLOCK_MSI_8MHZ
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bool "8MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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config CLOCK_MSI_16MHZ
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bool "16MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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config CLOCK_MSI_24MHZ
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bool "24MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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config CLOCK_MSI_32MHZ
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bool "32MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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config CLOCK_MSI_48MHZ
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bool "48MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
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endchoice
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config CLOCK_MSI
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int
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default 65536 if CLOCK_MSI_65KHZ
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default 131072 if CLOCK_MSI_130KHZ
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default 262144 if CLOCK_MSI_260KHZ
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default 524288 if CLOCK_MSI_520KHZ
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default 100000 if CLOCK_MSI_100KHZ
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default 200000 if CLOCK_MSI_200KHZ
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default 400000 if CLOCK_MSI_400KHZ
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default 800000 if CLOCK_MSI_800KHZ
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default 1000000 if CLOCK_MSI_1MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL)
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default 1048000 if CLOCK_MSI_1MHZ && (CPU_FAM_L0 || CPU_FAM_L1)
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default 2000000 if CLOCK_MSI_2MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL)
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default 2097000 if CLOCK_MSI_2MHZ && (CPU_FAM_L0 || CPU_FAM_L1)
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default 4000000 if CLOCK_MSI_4MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL)
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default 4194000 if CLOCK_MSI_4MHZ && (CPU_FAM_L0 || CPU_FAM_L1)
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default 8000000 if CLOCK_MSI_8MHZ
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default 16000000 if CLOCK_MSI_16MHZ
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default 24000000 if CLOCK_MSI_24MHZ
|
||||
default 32000000 if CLOCK_MSI_32MHZ
|
||||
default 48000000 if CLOCK_MSI_48MHZ
|
||||
|
||||
endif # CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
choice
|
||||
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
|
||||
default CLOCK_APB1_DIV_4 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_U5 || CPU_FAM_WB || CPU_FAM_WL
|
||||
@ -433,87 +98,3 @@ config CLOCK_APB2_DIV
|
||||
default 4 if CLOCK_APB2_DIV_4
|
||||
default 8 if CLOCK_APB2_DIV_8
|
||||
default 16 if CLOCK_APB2_DIV_16
|
||||
|
||||
if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
config CLOCK_ENABLE_MCO
|
||||
bool "Enable MCU Clock Output (MCO) on PA8"
|
||||
|
||||
choice
|
||||
bool "MCO source"
|
||||
depends on CLOCK_ENABLE_MCO
|
||||
default CLOCK_MCO_USE_PLLCLK
|
||||
|
||||
config CLOCK_MCO_USE_PLLCLK
|
||||
bool "Use PLLCLK as MCO source"
|
||||
|
||||
config CLOCK_MCO_USE_HSE
|
||||
bool "Use HSE as MCO source"
|
||||
|
||||
config CLOCK_MCO_USE_HSI
|
||||
bool "Use HSI as MCO source"
|
||||
|
||||
config CLOCK_MCO_USE_LSE
|
||||
bool "Use LSE as MCO source"
|
||||
depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
config CLOCK_MCO_USE_LSI
|
||||
bool "Use LSI as MCO source"
|
||||
depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
config CLOCK_MCO_USE_MSI
|
||||
bool "Use MSI as MCO source"
|
||||
depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
config CLOCK_MCO_USE_SYSCLK
|
||||
bool "Use SYSCLK as MCO source"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
bool "MCO prescaler"
|
||||
depends on !CLOCK_HAS_NO_MCO_PRE && CLOCK_ENABLE_MCO
|
||||
default CLOCK_MCO_PRE_1
|
||||
|
||||
config CLOCK_MCO_PRE_1
|
||||
bool "Divide MCO by 1"
|
||||
|
||||
config CLOCK_MCO_PRE_2
|
||||
bool "Divide MCO by 2"
|
||||
|
||||
config CLOCK_MCO_PRE_4
|
||||
bool "Divide MCO by 4"
|
||||
|
||||
config CLOCK_MCO_PRE_8
|
||||
bool "Divide MCO by 8"
|
||||
|
||||
config CLOCK_MCO_PRE_16
|
||||
bool "Divide MCO by 16"
|
||||
|
||||
config CLOCK_MCO_PRE_32
|
||||
bool "Divide MCO by 32"
|
||||
depends on !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB && !CPU_FAM_WL
|
||||
|
||||
config CLOCK_MCO_PRE_64
|
||||
bool "Divide MCO by 64"
|
||||
depends on !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB && !CPU_FAM_WL
|
||||
|
||||
config CLOCK_MCO_PRE_128
|
||||
bool "Divide MCO by 128"
|
||||
depends on !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB && !CPU_FAM_WL
|
||||
|
||||
endchoice
|
||||
|
||||
config CLOCK_MCO_PRE
|
||||
int
|
||||
default 2 if CLOCK_MCO_PRE_2
|
||||
default 4 if CLOCK_MCO_PRE_4
|
||||
default 8 if CLOCK_MCO_PRE_8
|
||||
default 16 if CLOCK_MCO_PRE_16
|
||||
default 32 if CLOCK_MCO_PRE_32
|
||||
default 64 if CLOCK_MCO_PRE_64
|
||||
default 128 if CLOCK_MCO_PRE_128
|
||||
default 1
|
||||
|
||||
endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
endmenu
|
||||
|
||||
8
cpu/stm32/kconfigs/f0/Kconfig.clk
Normal file
8
cpu/stm32/kconfigs/f0/Kconfig.clk
Normal file
@ -0,0 +1,8 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../f0f1f3/Kconfig.clk'
|
||||
@ -28,6 +28,7 @@ config CPU_LINE_STM32F031X6
|
||||
select CPU_FAM_F0
|
||||
select HAS_PERIPH_RTC_MEM
|
||||
select HAS_PERIPH_VBAT
|
||||
select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
|
||||
config CPU_LINE_STM32F038XX
|
||||
bool
|
||||
@ -40,6 +41,7 @@ config CPU_LINE_STM32F042X6
|
||||
select CPU_FAM_F0
|
||||
select HAS_PERIPH_RTC_MEM
|
||||
select HAS_PERIPH_VBAT
|
||||
select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
|
||||
config CPU_LINE_STM32F048XX
|
||||
bool
|
||||
|
||||
31
cpu/stm32/kconfigs/f0f1f3/Kconfig.clk
Normal file
31
cpu/stm32/kconfigs/f0f1f3/Kconfig.clk
Normal file
@ -0,0 +1,31 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3
|
||||
|
||||
config CLOCK_PLL_PREDIV
|
||||
int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
default 2 if HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2 || CLOCK_HSE = 16000000
|
||||
default 1
|
||||
range 1 16
|
||||
|
||||
config CLOCK_PLL_MUL
|
||||
int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 12 if CPU_FAM_F0 && HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
default 6 if CPU_FAM_F0
|
||||
default 16 if CPU_FAM_F3 && HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
default 9 if CPU_FAM_F1 || CPU_FAM_F3
|
||||
|
||||
range 2 16
|
||||
|
||||
config HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
bool
|
||||
help
|
||||
Indicated that this CPU Line has the prediv hardwired to 2, making it
|
||||
unable to change.
|
||||
|
||||
endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3
|
||||
89
cpu/stm32/kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk
Normal file
89
cpu/stm32/kconfigs/f0f1f3g0g4l0l1l4wbwl/Kconfig.clk
Normal file
@ -0,0 +1,89 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
config CLOCK_ENABLE_MCO
|
||||
bool "Enable MCU Clock Output (MCO) on PA8"
|
||||
|
||||
choice
|
||||
bool "MCO source"
|
||||
depends on CLOCK_ENABLE_MCO
|
||||
default CLOCK_MCO_USE_PLLCLK
|
||||
|
||||
config CLOCK_MCO_USE_PLLCLK
|
||||
bool "Use PLLCLK as MCO source"
|
||||
|
||||
config CLOCK_MCO_USE_HSE
|
||||
bool "Use HSE as MCO source"
|
||||
|
||||
config CLOCK_MCO_USE_HSI
|
||||
bool "Use HSI as MCO source"
|
||||
|
||||
config CLOCK_MCO_USE_LSE
|
||||
bool "Use LSE as MCO source"
|
||||
depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
config CLOCK_MCO_USE_LSI
|
||||
bool "Use LSI as MCO source"
|
||||
depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
config CLOCK_MCO_USE_MSI
|
||||
bool "Use MSI as MCO source"
|
||||
depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
config CLOCK_MCO_USE_SYSCLK
|
||||
bool "Use SYSCLK as MCO source"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
bool "MCO prescaler"
|
||||
depends on !CLOCK_HAS_NO_MCO_PRE && CLOCK_ENABLE_MCO
|
||||
default CLOCK_MCO_PRE_1
|
||||
|
||||
config CLOCK_MCO_PRE_1
|
||||
bool "Divide MCO by 1"
|
||||
|
||||
config CLOCK_MCO_PRE_2
|
||||
bool "Divide MCO by 2"
|
||||
|
||||
config CLOCK_MCO_PRE_4
|
||||
bool "Divide MCO by 4"
|
||||
|
||||
config CLOCK_MCO_PRE_8
|
||||
bool "Divide MCO by 8"
|
||||
|
||||
config CLOCK_MCO_PRE_16
|
||||
bool "Divide MCO by 16"
|
||||
|
||||
config CLOCK_MCO_PRE_32
|
||||
bool "Divide MCO by 32"
|
||||
depends on CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0
|
||||
|
||||
config CLOCK_MCO_PRE_64
|
||||
bool "Divide MCO by 64"
|
||||
depends on CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0
|
||||
|
||||
config CLOCK_MCO_PRE_128
|
||||
bool "Divide MCO by 128"
|
||||
depends on CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0
|
||||
|
||||
endchoice
|
||||
|
||||
config CLOCK_MCO_PRE
|
||||
int
|
||||
default 2 if CLOCK_MCO_PRE_2
|
||||
default 4 if CLOCK_MCO_PRE_4
|
||||
default 8 if CLOCK_MCO_PRE_8
|
||||
default 16 if CLOCK_MCO_PRE_16
|
||||
default 32 if CLOCK_MCO_PRE_32
|
||||
default 64 if CLOCK_MCO_PRE_64
|
||||
default 128 if CLOCK_MCO_PRE_128
|
||||
default 1
|
||||
|
||||
endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L4 || CPU_FAM_WB || CPU_FAM_WL
|
||||
8
cpu/stm32/kconfigs/f1/Kconfig.clk
Normal file
8
cpu/stm32/kconfigs/f1/Kconfig.clk
Normal file
@ -0,0 +1,8 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../f0f1f3/Kconfig.clk'
|
||||
22
cpu/stm32/kconfigs/f2/Kconfig.clk
Normal file
22
cpu/stm32/kconfigs/f2/Kconfig.clk
Normal file
@ -0,0 +1,22 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../f2f4f7mp1/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_F2
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 4
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 120 if CLOCK_HSE = 8000000
|
||||
default 60
|
||||
range 50 432
|
||||
|
||||
endif # CPU_FAM_F2
|
||||
54
cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk
Normal file
54
cpu/stm32/kconfigs/f2f4f7mp1/Kconfig.clk
Normal file
@ -0,0 +1,54 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1
|
||||
|
||||
choice
|
||||
bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS
|
||||
default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
|
||||
default PLL_P_DIV_2
|
||||
|
||||
config PLL_P_DIV_2
|
||||
bool "Divide by 2"
|
||||
|
||||
config PLL_P_DIV_4
|
||||
bool "Divide by 4"
|
||||
|
||||
config PLL_P_DIV_6
|
||||
bool "Divide by 6"
|
||||
|
||||
config PLL_P_DIV_8
|
||||
bool "Divide by 8"
|
||||
|
||||
endchoice
|
||||
|
||||
config CLOCK_PLL_P
|
||||
int
|
||||
default 3 if CPU_FAM_MP1
|
||||
default 2 if PLL_P_DIV_2
|
||||
default 4 if PLL_P_DIV_4
|
||||
default 6 if PLL_P_DIV_6
|
||||
default 8 if PLL_P_DIV_8
|
||||
|
||||
config CLOCK_PLL_Q
|
||||
int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS
|
||||
default 5 if CPU_FAM_F2
|
||||
default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
|
||||
default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ
|
||||
default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
|
||||
default 9 if CPU_FAM_F7
|
||||
default 13 if CPU_FAM_MP1
|
||||
default 8
|
||||
range 2 15
|
||||
|
||||
config HAVE_CLOCK_ALT_48MHZ
|
||||
bool
|
||||
help
|
||||
Indicates this CPU has an alternate clock source that can be used to
|
||||
provide 48 MHz for the USB peripheral.
|
||||
|
||||
endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1
|
||||
8
cpu/stm32/kconfigs/f3/Kconfig.clk
Normal file
8
cpu/stm32/kconfigs/f3/Kconfig.clk
Normal file
@ -0,0 +1,8 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../f0f1f3/Kconfig.clk'
|
||||
@ -27,15 +27,27 @@ config CPU_LINE_STM32F302XE
|
||||
bool
|
||||
select CPU_FAM_F3
|
||||
|
||||
config CPU_LINE_STM32F303X6
|
||||
bool
|
||||
select CPU_FAM_F3
|
||||
select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
|
||||
config CPU_LINE_STM32F303X8
|
||||
bool
|
||||
select CPU_FAM_F3
|
||||
select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
|
||||
config CPU_LINE_STM32F303XB
|
||||
bool
|
||||
select CPU_FAM_F3
|
||||
select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
|
||||
config CPU_LINE_STM32F303XC
|
||||
bool
|
||||
select CPU_FAM_F3
|
||||
select HAS_CORTEXM_MPU
|
||||
select CLOCK_HAS_NO_MCO_PRE
|
||||
select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
|
||||
config CPU_LINE_STM32F303XE
|
||||
bool
|
||||
@ -49,6 +61,7 @@ config CPU_LINE_STM32F318XX
|
||||
config CPU_LINE_STM32F328XX
|
||||
bool
|
||||
select CPU_FAM_F3
|
||||
select HAVE_CLOCK_PLL_PREDIV_HARDWIRED_2
|
||||
|
||||
config CPU_LINE_STM32F334X8
|
||||
bool
|
||||
|
||||
43
cpu/stm32/kconfigs/f4/Kconfig.clk
Normal file
43
cpu/stm32/kconfigs/f4/Kconfig.clk
Normal file
@ -0,0 +1,43 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../f2f4f7mp1/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_F4
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 25 if CLOCK_MAX_84MHZ && CLOCK_HSE = 25000000
|
||||
default 25 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000
|
||||
default 12 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000
|
||||
default 12 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000
|
||||
default 4
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 168 if CLOCK_MAX_84MHZ && CLOCK_HSE = 8000000
|
||||
default 336 if CLOCK_MAX_84MHZ && CLOCK_HSE = 25000000
|
||||
default 84 if CLOCK_MAX_84MHZ
|
||||
|
||||
default 96 if CLOCK_MAX_100MHZ && CLOCK_HSE = 8000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
|
||||
default 100 if CLOCK_MAX_100MHZ && CLOCK_HSE = 8000000
|
||||
default 192 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
|
||||
default 200 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000
|
||||
default 48 if CLOCK_MAX_100MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK)
|
||||
default 50 if CLOCK_MAX_100MHZ
|
||||
|
||||
default 168 if CLOCK_MAX_180MHZ && CLOCK_HSE = 8000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
|
||||
default 180 if CLOCK_MAX_180MHZ && CLOCK_HSE = 8000000
|
||||
default 336 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
|
||||
default 360 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000
|
||||
default 336 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
|
||||
default 360 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000
|
||||
default 84 if CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
|
||||
default 90 if CLOCK_MAX_180MHZ
|
||||
range 50 432
|
||||
|
||||
endif # CPU_FAM_F4
|
||||
@ -59,28 +59,33 @@ config CPU_LINE_STM32F412CX
|
||||
bool
|
||||
select CPU_FAM_F4
|
||||
select CLOCK_MAX_100MHZ
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
config CPU_LINE_STM32F412RX
|
||||
bool
|
||||
select CPU_FAM_F4
|
||||
select CLOCK_MAX_100MHZ
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
config CPU_LINE_STM32F412VX
|
||||
bool
|
||||
select CPU_FAM_F4
|
||||
select CLOCK_MAX_100MHZ
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
config CPU_LINE_STM32F412ZX
|
||||
bool
|
||||
select CPU_FAM_F4
|
||||
select HAS_PERIPH_HWRNG
|
||||
select CLOCK_MAX_100MHZ
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
config CPU_LINE_STM32F413XX
|
||||
bool
|
||||
select CPU_FAM_F4
|
||||
select HAS_PERIPH_HWRNG
|
||||
select CLOCK_MAX_100MHZ
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
config CPU_LINE_STM32F415XX
|
||||
bool
|
||||
@ -99,6 +104,7 @@ config CPU_LINE_STM32F423XX
|
||||
bool
|
||||
select CPU_FAM_F4
|
||||
select CLOCK_MAX_100MHZ
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
config CPU_LINE_STM32F427XX
|
||||
bool
|
||||
@ -132,6 +138,7 @@ config CPU_LINE_STM32F446XX
|
||||
select CPU_FAM_F4
|
||||
select HAS_BACKUP_RAM
|
||||
select CLOCK_MAX_180MHZ
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
config CPU_LINE_STM32F469XX
|
||||
bool
|
||||
@ -139,9 +146,11 @@ config CPU_LINE_STM32F469XX
|
||||
select HAS_BACKUP_RAM
|
||||
select HAS_PERIPH_HWRNG
|
||||
select CLOCK_MAX_180MHZ
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
config CPU_LINE_STM32F479XX
|
||||
bool
|
||||
select CPU_FAM_F4
|
||||
select HAS_BACKUP_RAM
|
||||
select CLOCK_MAX_180MHZ
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
@ -22,6 +22,7 @@ config CPU_FAM_F7
|
||||
select HAS_PERIPH_VBAT
|
||||
select HAS_PERIPH_WDT
|
||||
select HAS_BOOTLOADER_STM32
|
||||
select HAVE_CLOCK_ALT_48MHZ
|
||||
|
||||
config CPU_FAM
|
||||
default "f7" if CPU_FAM_F7
|
||||
|
||||
24
cpu/stm32/kconfigs/f7/Kconfig.clk
Normal file
24
cpu/stm32/kconfigs/f7/Kconfig.clk
Normal file
@ -0,0 +1,24 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../f2f4f7mp1/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_F7
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 25 if CLOCK_HSE = 25000000
|
||||
default 4
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 216 if CLOCK_HSE = 8000000
|
||||
default 432 if CLOCK_HSE = 25000000
|
||||
default 108
|
||||
range 50 432
|
||||
|
||||
endif # CPU_FAM_F7
|
||||
63
cpu/stm32/kconfigs/g0/Kconfig.clk
Normal file
63
cpu/stm32/kconfigs/g0/Kconfig.clk
Normal file
@ -0,0 +1,63 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../g0wxmp1/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_G0
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 1
|
||||
range 1 8
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 20
|
||||
range 8 86
|
||||
|
||||
choice
|
||||
bool "HSISYS division factor" if USE_CLOCK_HSI
|
||||
default CLOCK_HSISYS_DIV_1
|
||||
|
||||
config CLOCK_HSISYS_DIV_1
|
||||
bool "Divide HSISYS by 1"
|
||||
|
||||
config CLOCK_HSISYS_DIV_2
|
||||
bool "Divide HSISYS by 2"
|
||||
|
||||
config CLOCK_HSISYS_DIV_4
|
||||
bool "Divide HSISYS by 4"
|
||||
|
||||
config CLOCK_HSISYS_DIV_8
|
||||
bool "Divide HSISYS by 8"
|
||||
|
||||
config CLOCK_HSISYS_DIV_16
|
||||
bool "Divide HSISYS by 16"
|
||||
|
||||
config CLOCK_HSISYS_DIV_32
|
||||
bool "Divide HSISYS by 32"
|
||||
|
||||
config CLOCK_HSISYS_DIV_64
|
||||
bool "Divide HSISYS by 64"
|
||||
|
||||
config CLOCK_HSISYS_DIV_128
|
||||
bool "Divide HSISYS by 128"
|
||||
|
||||
endchoice
|
||||
|
||||
config CLOCK_HSISYS_DIV
|
||||
int
|
||||
default 1 if CLOCK_HSISYS_DIV_1
|
||||
default 2 if CLOCK_HSISYS_DIV_2
|
||||
default 4 if CLOCK_HSISYS_DIV_4
|
||||
default 8 if CLOCK_HSISYS_DIV_8
|
||||
default 16 if CLOCK_HSISYS_DIV_16
|
||||
default 32 if CLOCK_HSISYS_DIV_32
|
||||
default 64 if CLOCK_HSISYS_DIV_64
|
||||
default 128 if CLOCK_HSISYS_DIV_128
|
||||
|
||||
endif # CPU_FAM_G0
|
||||
18
cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk
Normal file
18
cpu/stm32/kconfigs/g0wxmp1/Kconfig.clk
Normal file
@ -0,0 +1,18 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
if CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1
|
||||
|
||||
config CLOCK_PLL_R
|
||||
int "Q: VCO division factor" if CUSTOM_PLL_PARAMS
|
||||
default 2 if CPU_FAM_WB || CPU_FAM_WL
|
||||
default 3 if CPU_FAM_MP1
|
||||
default 6 if BOARD_HAS_HSE
|
||||
default 5
|
||||
range 2 8
|
||||
|
||||
endif # CPU_FAM_G0 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1
|
||||
23
cpu/stm32/kconfigs/g4/Kconfig.clk
Normal file
23
cpu/stm32/kconfigs/g4/Kconfig.clk
Normal file
@ -0,0 +1,23 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../g4l4l5/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_G4
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 6 if BOARD_HAS_HSE
|
||||
default 4
|
||||
range 1 16
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 85
|
||||
range 8 127
|
||||
|
||||
endif # CPU_FAM_G4
|
||||
35
cpu/stm32/kconfigs/g4l4l5/Kconfig.clk
Normal file
35
cpu/stm32/kconfigs/g4l4l5/Kconfig.clk
Normal file
@ -0,0 +1,35 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
if CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
|
||||
|
||||
choice
|
||||
bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if CUSTOM_PLL_PARAMS
|
||||
default PLL_R_DIV_2
|
||||
|
||||
config PLL_R_DIV_2
|
||||
bool "Divide by 2"
|
||||
|
||||
config PLL_R_DIV_4
|
||||
bool "Divide by 4"
|
||||
|
||||
config PLL_R_DIV_6
|
||||
bool "Divide by 6"
|
||||
|
||||
config PLL_R_DIV_8
|
||||
bool "Divide by 8"
|
||||
|
||||
endchoice
|
||||
|
||||
config CLOCK_PLL_R
|
||||
int
|
||||
default 2 if PLL_R_DIV_2
|
||||
default 4 if PLL_R_DIV_4
|
||||
default 6 if PLL_R_DIV_6
|
||||
default 8 if PLL_R_DIV_8
|
||||
|
||||
endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
|
||||
8
cpu/stm32/kconfigs/l0/Kconfig.clk
Normal file
8
cpu/stm32/kconfigs/l0/Kconfig.clk
Normal file
@ -0,0 +1,8 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../l0l1/Kconfig.clk'
|
||||
112
cpu/stm32/kconfigs/l0l1/Kconfig.clk
Normal file
112
cpu/stm32/kconfigs/l0l1/Kconfig.clk
Normal file
@ -0,0 +1,112 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
if CPU_FAM_L0 || CPU_FAM_L1
|
||||
|
||||
config CLOCK_PLL_DIV
|
||||
int "Main PLL division factor" if CUSTOM_PLL_PARAMS
|
||||
default 2
|
||||
range 2 4
|
||||
|
||||
choice
|
||||
bool "Main PLL multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default PLL_MUL_4
|
||||
|
||||
config PLL_MUL_3
|
||||
bool "Multiply by 3"
|
||||
|
||||
config PLL_MUL_4
|
||||
bool "Multiply by 4"
|
||||
|
||||
config PLL_MUL_6
|
||||
bool "Multiply by 6"
|
||||
|
||||
config PLL_MUL_8
|
||||
bool "Multiply by 8"
|
||||
|
||||
config PLL_MUL_12
|
||||
bool "Multiply by 12"
|
||||
|
||||
config PLL_MUL_16
|
||||
bool "Multiply by 16"
|
||||
|
||||
config PLL_MUL_24
|
||||
bool "Multiply by 24"
|
||||
|
||||
config PLL_MUL_32
|
||||
bool "Multiply by 32"
|
||||
|
||||
config PLL_MUL_48
|
||||
bool "Multiply by 48"
|
||||
|
||||
endchoice
|
||||
|
||||
config CLOCK_PLL_MUL
|
||||
int
|
||||
default 3 if PLL_MUL_3
|
||||
default 4 if PLL_MUL_4
|
||||
default 6 if PLL_MUL_6
|
||||
default 8 if PLL_MUL_8
|
||||
default 12 if PLL_MUL_12
|
||||
default 16 if PLL_MUL_16
|
||||
default 24 if PLL_MUL_24
|
||||
default 32 if PLL_MUL_32
|
||||
default 48 if PLL_MUL_48
|
||||
|
||||
config USE_CLOCK_MSI
|
||||
bool "Use direct multi-speed frequency internal oscillator (MSI)"
|
||||
|
||||
choice
|
||||
bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI)
|
||||
default CLOCK_MSI_4MHZ
|
||||
|
||||
config CLOCK_MSI_65KHZ
|
||||
bool "65.536kHz"
|
||||
|
||||
config CLOCK_MSI_130KHZ
|
||||
bool "131.072kHz"
|
||||
|
||||
config CLOCK_MSI_260KHZ
|
||||
bool "262.144kHz"
|
||||
|
||||
config CLOCK_MSI_520KHZ
|
||||
bool "524.288kHz"
|
||||
|
||||
config CLOCK_MSI_1MHZ
|
||||
bool
|
||||
prompt "1MHz"
|
||||
|
||||
config CLOCK_MSI_2MHZ
|
||||
bool
|
||||
prompt "2MHz"
|
||||
|
||||
config CLOCK_MSI_4MHZ
|
||||
bool
|
||||
prompt "4MHz"
|
||||
|
||||
endchoice
|
||||
|
||||
config CLOCK_MSI
|
||||
int
|
||||
default 65536 if CLOCK_MSI_65KHZ
|
||||
default 131072 if CLOCK_MSI_130KHZ
|
||||
default 262144 if CLOCK_MSI_260KHZ
|
||||
default 524288 if CLOCK_MSI_520KHZ
|
||||
default 100000 if CLOCK_MSI_100KHZ
|
||||
default 200000 if CLOCK_MSI_200KHZ
|
||||
default 400000 if CLOCK_MSI_400KHZ
|
||||
default 800000 if CLOCK_MSI_800KHZ
|
||||
default 1048000 if CLOCK_MSI_1MHZ
|
||||
default 2097000 if CLOCK_MSI_2MHZ
|
||||
default 4194000 if CLOCK_MSI_4MHZ
|
||||
default 8000000 if CLOCK_MSI_8MHZ
|
||||
default 16000000 if CLOCK_MSI_16MHZ
|
||||
default 24000000 if CLOCK_MSI_24MHZ
|
||||
default 32000000 if CLOCK_MSI_32MHZ
|
||||
default 48000000 if CLOCK_MSI_48MHZ
|
||||
|
||||
endif # CPU_FAM_L0 || CPU_FAM_L1
|
||||
8
cpu/stm32/kconfigs/l1/Kconfig.clk
Normal file
8
cpu/stm32/kconfigs/l1/Kconfig.clk
Normal file
@ -0,0 +1,8 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../l0l1/Kconfig.clk'
|
||||
25
cpu/stm32/kconfigs/l4/Kconfig.clk
Normal file
25
cpu/stm32/kconfigs/l4/Kconfig.clk
Normal file
@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../g4l4l5/Kconfig.clk'
|
||||
rsource '../l4l5wx/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_L4
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 6 if CLOCK_PLL_SRC_MSI
|
||||
default 2
|
||||
range 1 8
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX
|
||||
default 20
|
||||
range 8 86
|
||||
|
||||
endif # CPU_FAM_L4
|
||||
94
cpu/stm32/kconfigs/l4l5wx/Kconfig.clk
Normal file
94
cpu/stm32/kconfigs/l4l5wx/Kconfig.clk
Normal file
@ -0,0 +1,94 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
|
||||
|
||||
config USE_CLOCK_MSI
|
||||
bool "Use direct multi-speed frequency internal oscillator (MSI)"
|
||||
|
||||
choice
|
||||
bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI)
|
||||
default CLOCK_MSI_48MHZ
|
||||
|
||||
config CLOCK_MSI_100KHZ
|
||||
bool "100kHz"
|
||||
|
||||
config CLOCK_MSI_200KHZ
|
||||
bool "200kHz"
|
||||
|
||||
config CLOCK_MSI_400KHZ
|
||||
bool "400kHz"
|
||||
|
||||
config CLOCK_MSI_800KHZ
|
||||
bool "800kHz"
|
||||
|
||||
config CLOCK_MSI_1MHZ
|
||||
bool
|
||||
prompt "1MHz"
|
||||
|
||||
config CLOCK_MSI_2MHZ
|
||||
bool
|
||||
prompt "2MHz"
|
||||
|
||||
config CLOCK_MSI_4MHZ
|
||||
bool
|
||||
prompt "4MHz"
|
||||
|
||||
config CLOCK_MSI_8MHZ
|
||||
bool "8MHz"
|
||||
|
||||
config CLOCK_MSI_16MHZ
|
||||
bool "16MHz"
|
||||
|
||||
config CLOCK_MSI_24MHZ
|
||||
bool "24MHz"
|
||||
|
||||
config CLOCK_MSI_32MHZ
|
||||
bool "32MHz"
|
||||
|
||||
config CLOCK_MSI_48MHZ
|
||||
bool "48MHz"
|
||||
|
||||
endchoice
|
||||
|
||||
config CLOCK_MSI
|
||||
int
|
||||
default 65536 if CLOCK_MSI_65KHZ
|
||||
default 131072 if CLOCK_MSI_130KHZ
|
||||
default 262144 if CLOCK_MSI_260KHZ
|
||||
default 524288 if CLOCK_MSI_520KHZ
|
||||
default 100000 if CLOCK_MSI_100KHZ
|
||||
default 200000 if CLOCK_MSI_200KHZ
|
||||
default 400000 if CLOCK_MSI_400KHZ
|
||||
default 800000 if CLOCK_MSI_800KHZ
|
||||
default 1000000 if CLOCK_MSI_1MHZ
|
||||
default 2000000 if CLOCK_MSI_2MHZ
|
||||
default 4000000 if CLOCK_MSI_4MHZ
|
||||
default 8000000 if CLOCK_MSI_8MHZ
|
||||
default 16000000 if CLOCK_MSI_16MHZ
|
||||
default 24000000 if CLOCK_MSI_24MHZ
|
||||
default 32000000 if CLOCK_MSI_32MHZ
|
||||
default 48000000 if CLOCK_MSI_48MHZ
|
||||
|
||||
|
||||
choice
|
||||
bool "Source clock for PLL" if USE_CLOCK_PLL
|
||||
default CLOCK_PLL_SRC_HSE if BOARD_HAS_HSE
|
||||
default CLOCK_PLL_SRC_MSI
|
||||
|
||||
config CLOCK_PLL_SRC_MSI
|
||||
bool "Use MSI source clock"
|
||||
|
||||
config CLOCK_PLL_SRC_HSE
|
||||
bool "Use HSE source clock"
|
||||
depends on BOARD_HAS_HSE
|
||||
|
||||
config CLOCK_PLL_SRC_HSI
|
||||
bool "Use HSI16 source clock"
|
||||
endchoice
|
||||
|
||||
endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB || CPU_FAM_WL
|
||||
24
cpu/stm32/kconfigs/l5/Kconfig.clk
Normal file
24
cpu/stm32/kconfigs/l5/Kconfig.clk
Normal file
@ -0,0 +1,24 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../g4l4l5/Kconfig.clk'
|
||||
rsource '../l4l5wx/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_L5
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 6 if CLOCK_PLL_SRC_MSI
|
||||
default 2
|
||||
range 1 8
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 27 if CPU_FAM_L5
|
||||
range 8 86
|
||||
|
||||
endif # CPU_FAM_L5
|
||||
24
cpu/stm32/kconfigs/mp1/Kconfig.clk
Normal file
24
cpu/stm32/kconfigs/mp1/Kconfig.clk
Normal file
@ -0,0 +1,24 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../f2f4f7mp1/Kconfig.clk'
|
||||
rsource '../g0wxmp1/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_MP1
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 2
|
||||
range 1 64
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 52 if BOARD_HAS_HSE
|
||||
default 78
|
||||
range 4 512
|
||||
|
||||
endif # CPU_FAM_MP1
|
||||
6
cpu/stm32/kconfigs/u5/Kconfig.clk
Normal file
6
cpu/stm32/kconfigs/u5/Kconfig.clk
Normal file
@ -0,0 +1,6 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
25
cpu/stm32/kconfigs/wb/Kconfig.clk
Normal file
25
cpu/stm32/kconfigs/wb/Kconfig.clk
Normal file
@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../l4l5wx/Kconfig.clk'
|
||||
rsource '../g0wxmp1/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_WB
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 6 if CLOCK_PLL_SRC_MSI
|
||||
default 4 if CLOCK_PLL_SRC_HSE
|
||||
default 2
|
||||
range 1 8
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 16
|
||||
range 6 127
|
||||
|
||||
endif # CPU_FAM_WB
|
||||
25
cpu/stm32/kconfigs/wl/Kconfig.clk
Normal file
25
cpu/stm32/kconfigs/wl/Kconfig.clk
Normal file
@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2022 HAW Hamburg
|
||||
#
|
||||
# This file is subject to the terms and conditions of the GNU Lesser
|
||||
# General Public License v2.1. See the file LICENSE in the top level
|
||||
# directory for more details.
|
||||
#
|
||||
|
||||
rsource '../l4l5wx/Kconfig.clk'
|
||||
rsource '../g0wxmp1/Kconfig.clk'
|
||||
|
||||
if CPU_FAM_WL
|
||||
|
||||
config CLOCK_PLL_M
|
||||
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
|
||||
default 6 if CLOCK_PLL_SRC_MSI
|
||||
default 4 if CLOCK_PLL_SRC_HSE
|
||||
default 2
|
||||
range 1 8
|
||||
|
||||
config CLOCK_PLL_N
|
||||
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
|
||||
default 12
|
||||
range 6 127
|
||||
|
||||
endif # CPU_FAM_WL
|
||||
Loading…
Reference in New Issue
Block a user