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RIOT/cpu/stm32/kconfigs/f4/Kconfig.clk

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cpu/stm32/kconfig: rework clock tree This splits up the clock configs. It allows CPU_FAM based file sourcing and also common CPU_FAMs. The dependancies are also included in wildcards would be used for the CPU_FAM macro. This should be much more readable. This also takes into account the HSE speeds in order to match the make/header resolution. Some hidden symbols were added to make sorting many CPU_SERIES dependencies easier.
2022-10-26 11:55:43 +02:00
# Copyright (c) 2022 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
rsource '../f2f4f7mp1/Kconfig.clk'
if CPU_FAM_F4
config CLOCK_PLL_M
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
default 25 if CLOCK_MAX_84MHZ && CLOCK_HSE = 25000000
default 25 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000
default 12 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000
default 12 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000
default 4
config CLOCK_PLL_N
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
default 168 if CLOCK_MAX_84MHZ && CLOCK_HSE = 8000000
default 336 if CLOCK_MAX_84MHZ && CLOCK_HSE = 25000000
default 84 if CLOCK_MAX_84MHZ
default 96 if CLOCK_MAX_100MHZ && CLOCK_HSE = 8000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
default 100 if CLOCK_MAX_100MHZ && CLOCK_HSE = 8000000
default 192 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
default 200 if CLOCK_MAX_100MHZ && CLOCK_HSE = 25000000
default 48 if CLOCK_MAX_100MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK)
default 50 if CLOCK_MAX_100MHZ
default 168 if CLOCK_MAX_180MHZ && CLOCK_HSE = 8000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
default 180 if CLOCK_MAX_180MHZ && CLOCK_HSE = 8000000
default 336 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
default 360 if CLOCK_MAX_180MHZ && CLOCK_HSE = 12000000
default 336 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000 && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
default 360 if CLOCK_MAX_180MHZ && CLOCK_HSE = 16000000
default 84 if CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
default 90 if CLOCK_MAX_180MHZ
range 50 432
endif # CPU_FAM_F4
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