RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity
affa7e8081
RIOT/cpu/samd5x/cpu.c

245 lines
7.0 KiB
C
Raw Normal View History

cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
/*
* Copyright (C) 2019 ML!PA Consulting GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_samd5x
* @{
*
* @file cpu.c
* @brief Implementation of the CPU initialization for Microchip SAMD5x/SAME5x MCUs
*
* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
* @}
*/
#include "cpu.h"
#include "periph_conf.h"
#include "periph/init.h"
cpu: Moved stdio_init() into cpu_init() - Removed stdio_init() from newlib's _init(), as this is too late in the boot process to allow DEBUG()ing during periph_init() - Added stdio_init() to the various cpu_init() routines of the ARM CPUs just before periph_init()
2019-04-10 11:07:05 +02:00
#include "stdio_base.h"
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
2019-09-13 17:32:14 +02:00
#if CLOCK_CORECLOCK == 0
#error Please select CLOCK_CORECLOCK
#endif
/* use DFLL for low frequency operation */
#if CLOCK_CORECLOCK > SAM0_DFLL_FREQ_HZ
#define USE_DPLL 1
#else
#define USE_DPLL 0
#if (SAM0_DFLL_FREQ_HZ % CLOCK_CORECLOCK)
#error For frequencies < 48 MHz, CLOCK_CORECLOCK must be a divider of 48 MHz
#endif
#endif
/* If the CPU clock is lower than the minimal DPLL Freq
set fDPLL = 2 * CLOCK_CORECLOCK */
#if USE_DPLL && (CLOCK_CORECLOCK < SAM0_DPLL_FREQ_MIN_HZ)
#define DPLL_DIV 2
#else
#define DPLL_DIV 1
#endif
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
static void xosc32k_init(void)
{
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE
| OSC32KCTRL_XOSC32K_EN1K
| OSC32KCTRL_XOSC32K_EN32K
| OSC32KCTRL_XOSC32K_RUNSTDBY
| OSC32KCTRL_XOSC32K_XTALEN
| OSC32KCTRL_XOSC32K_STARTUP(7);
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {}
}
static void dfll_init(void)
{
uint32_t reg = OSCCTRL_DFLLCTRLB_QLDIS
#ifdef OSCCTRL_DFLLCTRLB_WAITLOCK
| OSCCTRL_DFLLCTRLB_WAITLOCK
#endif
;
cpu/samd5x: work around errata when (re-)initializing DFLL When a previously disabled DFLL gets enabled again, the frequency will be incorrect. Follow the procedure outlined in the errata sheet, section 2.8.3 to work around the issue. This fixes wake from standby.
2020-03-18 23:48:08 +01:00
/* workaround for Errata 2.8.3 DFLLVAL.FINE Value When DFLL48M Re-enabled */
OSCCTRL->DFLLMUL.reg = 0; /* Write new DFLLMULL configuration */
OSCCTRL->DFLLCTRLB.reg = 0; /* Select Open loop configuration */
OSCCTRL->DFLLCTRLA.bit.ENABLE = 1; /* Enable DFLL */
OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg; /* Reload DFLLVAL register */
OSCCTRL->DFLLCTRLB.reg = reg; /* Write final DFLL configuration */
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
cpu/samd5x: work around errata when (re-)initializing DFLL When a previously disabled DFLL gets enabled again, the frequency will be incorrect. Follow the procedure outlined in the errata sheet, section 2.8.3 to work around the issue. This fixes wake from standby.
2020-03-18 23:48:08 +01:00
OSCCTRL->DFLLCTRLA.reg = OSCCTRL_DFLLCTRLA_ENABLE;
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
while (!OSCCTRL->STATUS.bit.DFLLRDY) {}
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
}
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
2019-09-13 17:32:14 +02:00
#if USE_DPLL
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
static void fdpll0_init(uint32_t f_cpu)
{
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
/* We source the DPLL from 32kHz GCLK1 */
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
const uint32_t LDR = ((f_cpu << 5) / 32768);
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
/* disable the DPLL before changing the configuration */
OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 0;
while (OSCCTRL->Dpll[0].DPLLSYNCBUSY.reg) {}
/* set DPLL clock source */
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = GCLK_PCHCTRL_GEN(1) | GCLK_PCHCTRL_CHEN;
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
while (!(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg & GCLK_PCHCTRL_CHEN)) {}
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(LDR & 0x1F)
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
| OSCCTRL_DPLLRATIO_LDR((LDR >> 5) - 1);
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
/* Without LBYPASS, startup takes very long, see errata section 2.13. */
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
| OSCCTRL_DPLLCTRLB_WUF
| OSCCTRL_DPLLCTRLB_LBYPASS;
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
while (OSCCTRL->Dpll[0].DPLLSYNCBUSY.reg) {}
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
while (!(OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY &&
OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK)) {}
}
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
2019-09-13 17:32:14 +02:00
#endif
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
static void gclk_connect(uint8_t id, uint8_t src, uint32_t flags) {
GCLK->GENCTRL[id].reg = GCLK_GENCTRL_SRC(src) | GCLK_GENCTRL_GENEN | flags | GCLK_GENCTRL_IDC;
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(id)) {}
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
}
cpu/sam0: don't hard-code peripheral clocks Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK introduce helper functions to return the frequency of the individual GCLKs and use those for baud-rate calculations. This requires the GCLK to be part of the peripheral's config struct. While this is already the case for most peripherals, this also adds it for those where it wasn't used before. As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2019-12-16 19:40:23 +01:00
void sam0_gclk_enable(uint8_t id)
{
/* clocks 0 & 1 are always running */
switch (id) {
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
case SAM0_GCLK_8MHZ:
cpu/sam0: don't hard-code peripheral clocks Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK introduce helper functions to return the frequency of the individual GCLKs and use those for baud-rate calculations. This requires the GCLK to be part of the peripheral's config struct. While this is already the case for most peripherals, this also adds it for those where it wasn't used before. As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2019-12-16 19:40:23 +01:00
/* 8 MHz clock used by xtimer */
#if USE_DPLL
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
gclk_connect(SAM0_GCLK_8MHZ,
GCLK_SOURCE_DPLL0,
GCLK_GENCTRL_DIV(DPLL_DIV * CLOCK_CORECLOCK / 8000000));
cpu/sam0: don't hard-code peripheral clocks Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK introduce helper functions to return the frequency of the individual GCLKs and use those for baud-rate calculations. This requires the GCLK to be part of the peripheral's config struct. While this is already the case for most peripherals, this also adds it for those where it wasn't used before. As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2019-12-16 19:40:23 +01:00
#else
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
gclk_connect(SAM0_GCLK_8MHZ,
GCLK_SOURCE_DFLL,
GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / 8000000));
cpu/sam0: don't hard-code peripheral clocks Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK introduce helper functions to return the frequency of the individual GCLKs and use those for baud-rate calculations. This requires the GCLK to be part of the peripheral's config struct. While this is already the case for most peripherals, this also adds it for those where it wasn't used before. As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2019-12-16 19:40:23 +01:00
#endif
break;
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
case SAM0_GCLK_48MHZ:
gclk_connect(SAM0_GCLK_48MHZ, GCLK_SOURCE_DFLL, 0);
cpu/sam0: don't hard-code peripheral clocks Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK introduce helper functions to return the frequency of the individual GCLKs and use those for baud-rate calculations. This requires the GCLK to be part of the peripheral's config struct. While this is already the case for most peripherals, this also adds it for those where it wasn't used before. As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2019-12-16 19:40:23 +01:00
break;
}
}
uint32_t sam0_gclk_freq(uint8_t id)
{
switch (id) {
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
case SAM0_GCLK_MAIN:
cpu/sam0: don't hard-code peripheral clocks Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK introduce helper functions to return the frequency of the individual GCLKs and use those for baud-rate calculations. This requires the GCLK to be part of the peripheral's config struct. While this is already the case for most peripherals, this also adds it for those where it wasn't used before. As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2019-12-16 19:40:23 +01:00
return CLOCK_CORECLOCK;
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
case SAM0_GCLK_32KHZ:
cpu/sam0: don't hard-code peripheral clocks Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK introduce helper functions to return the frequency of the individual GCLKs and use those for baud-rate calculations. This requires the GCLK to be part of the peripheral's config struct. While this is already the case for most peripherals, this also adds it for those where it wasn't used before. As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2019-12-16 19:40:23 +01:00
return 32768;
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
case SAM0_GCLK_8MHZ:
cpu/sam0: don't hard-code peripheral clocks Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK introduce helper functions to return the frequency of the individual GCLKs and use those for baud-rate calculations. This requires the GCLK to be part of the peripheral's config struct. While this is already the case for most peripherals, this also adds it for those where it wasn't used before. As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2019-12-16 19:40:23 +01:00
return 8000000;
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
case SAM0_GCLK_48MHZ:
cpu/sam0: don't hard-code peripheral clocks Instead of hard-coding the peripheral clocks to CLOCK_CORECLOCK introduce helper functions to return the frequency of the individual GCLKs and use those for baud-rate calculations. This requires the GCLK to be part of the peripheral's config struct. While this is already the case for most peripherals, this also adds it for those where it wasn't used before. As it defaults to 0 (CLOCK_CORECLOCK) no change is to be expected.
2019-12-16 19:40:23 +01:00
return SAM0_DFLL_FREQ_HZ;
default:
return 0;
}
}
cpu/sam0_common: add cpu_pm_cb_enter()/leave() This allows to implement needed work-arounds surrounding sleep on a per-MCU basis.
2020-02-24 17:56:11 +01:00
void cpu_pm_cb_enter(int deep)
{
(void) deep;
/* will be called before entering sleep */
}
void cpu_pm_cb_leave(int deep)
{
/* will be called after wake-up */
cpu/samd5x: work around errata when (re-)initializing DFLL When a previously disabled DFLL gets enabled again, the frequency will be incorrect. Follow the procedure outlined in the errata sheet, section 2.8.3 to work around the issue. This fixes wake from standby.
2020-03-18 23:48:08 +01:00
if (deep) {
/* DFLL needs to be re-initialized to work around errata 2.8.3 */
dfll_init();
}
cpu/sam0_common: add cpu_pm_cb_enter()/leave() This allows to implement needed work-arounds surrounding sleep on a per-MCU basis.
2020-02-24 17:56:11 +01:00
}
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
/**
* @brief Initialize the CPU, set IRQ priorities, clocks
*/
void cpu_init(void)
{
cpu/samd5x: disable RTC on init to prevent undefined RTC state When changing the clock configuration while the RTC is running, the RTC may end up in an undefined state that leaves it unresponsive. The RTC is not reset to stay persistent across reboots/hibernate, so it will not be reset on init. Instead, disable the RTC while configuring the clocks, rtc_init() will take care of re-enabling it. @dylad introduced this workaround for saml21, samd5x needs it too. To reproduce, set the CLOCK_CORECLOCK of a samd5x board (e.g. same54-xpro) to 48 MHz. Run any RTC application. The CPU will be stuck in _wait_syncbusy() after a reboot. This patch will fix this. (You will need to power-cycle the board if the RTC has entered the stuck state as it will never be reset.)
2020-03-31 15:34:55 +02:00
/* Disable the RTC module to prevent synchronization issues during CPU init
if the RTC was running from a previous boot (e.g wakeup from backup) */
if (RTC->MODE2.CTRLA.bit.ENABLE) {
while (RTC->MODE2.SYNCBUSY.reg) {}
RTC->MODE2.CTRLA.bit.ENABLE = 0;
while (RTC->MODE2.SYNCBUSY.reg) {}
}
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
/* initialize the Cortex-M core */
cortexm_init();
/* turn on only needed APB peripherals */
MCLK->APBAMASK.reg = MCLK_APBAMASK_MCLK
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
| MCLK_APBAMASK_OSCCTRL
| MCLK_APBAMASK_OSC32KCTRL
| MCLK_APBAMASK_GCLK
| MCLK_APBAMASK_SUPC
| MCLK_APBAMASK_PAC
#ifdef MODULE_PERIPH_PM
| MCLK_APBAMASK_PM
#endif
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
#ifdef MODULE_PERIPH_GPIO_IRQ
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
| MCLK_APBAMASK_EIC
#endif
;
MCLK->APBBMASK.reg = 0
#ifdef MODULE_PERIPH_FLASHPAGE
| MCLK_APBBMASK_NVMCTRL
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
#endif
#ifdef MODULE_PERIPH_GPIO
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
| MCLK_APBBMASK_PORT
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
#endif
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
;
MCLK->APBCMASK.reg = 0;
MCLK->APBDMASK.reg = 0;
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
/* enable the Cortex M Cache Controller */
CMCC->CTRL.bit.CEN = 1;
xosc32k_init();
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
gclk_connect(SAM0_GCLK_32KHZ, GCLK_SOURCE_XOSC32K, 0);
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
/* make sure main clock is not sourced from DPLL */
dfll_init();
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DFLL, 0);
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
2019-09-13 17:32:14 +02:00
#if USE_DPLL
fdpll0_init(CLOCK_CORECLOCK * DPLL_DIV);
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
cpu/samd5x: fix CPU init There were still some things wrong with samd5x CPU init which only showed up when used in conjunction with RIOTBOOT, that is cpu_init() was called twice. - gclk_connect() should block until the GCLK is ready. - DPLL should be disabled dring configuration. - make sure not to use DPLL for MCLK when re-configuring DPLL - All APBxMASK bits should be in a defined state. - always enable 1kHz oscilator output.
2019-06-06 19:51:48 +02:00
/* source main clock from DPLL */
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DPLL0, GCLK_GENCTRL_DIV(DPLL_DIV));
cpu/samd5x: allow more flexible selection of CLOCK_CORECLOCK There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
2019-09-13 17:32:14 +02:00
#else
cpu/sam0: use defines for GCLK IDs Give the clocks explicit names to better identify their meaning.
2019-12-16 19:41:16 +01:00
gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DFLL, GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / CLOCK_CORECLOCK));
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
#endif
cpu/samd5x: Add DMA peripheral to init
2020-06-11 11:05:51 +02:00
#ifdef MODULE_PERIPH_DMA
/* initialize DMA streams */
dma_init();
#endif
cpu: Moved stdio_init() into cpu_init() - Removed stdio_init() from newlib's _init(), as this is too late in the boot process to allow DEBUG()ing during periph_init() - Added stdio_init() to the various cpu_init() routines of the ARM CPUs just before periph_init()
2019-04-10 11:07:05 +02:00
/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
stdio_init();
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
/* trigger static peripheral initialization */
periph_init();
cpu/samd5x: use ONDEMAND bit to run clocks on demand Set the ONDEMAND bit so clocks are only run if they have a user configured. This saves 390 µA on same54-xpro. examples/default: before: 3.88 mA after : 3.49 mA examples/gnrc_networking: (with REB215-XPRO EXT3) before: 13.29 mA after : 12.9 mA
2020-02-19 16:29:44 +01:00
/* set ONDEMAND bit after all clocks have been configured */
/* This is to avoid setting the source for the main clock to ONDEMAND before using it. */
OSCCTRL->Dpll[0].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
cpu/samd5x: add support for samd5x/same5x MCUs This adds supoprt for the Atmel SAMD51 & SAME54 SoC. The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
2019-03-12 13:57:27 +01:00
}
Copy Permalink