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75 lines
4.1 KiB
C
75 lines
4.1 KiB
C
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/**
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* \file
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*
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* \brief Instance description for OSC32KCTRL
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_OSC32KCTRL_INSTANCE_
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#define _SAML21_OSC32KCTRL_INSTANCE_
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/* ========== Register definition for OSC32KCTRL peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_OSC32KCTRL_INTENCLR (0x40001000U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
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#define REG_OSC32KCTRL_INTENSET (0x40001004U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
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#define REG_OSC32KCTRL_INTFLAG (0x40001008U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
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#define REG_OSC32KCTRL_STATUS (0x4000100CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */
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#define REG_OSC32KCTRL_RTCCTRL (0x40001010U) /**< \brief (OSC32KCTRL) Clock selection */
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#define REG_OSC32KCTRL_XOSC32K (0x40001014U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
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#define REG_OSC32KCTRL_OSC32K (0x40001018U) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */
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#define REG_OSC32KCTRL_OSCULP32K (0x4000101CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
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#else
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#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001000U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
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#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001004U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
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#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001008U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
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#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000100CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */
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#define REG_OSC32KCTRL_RTCCTRL (*(RwReg *)0x40001010U) /**< \brief (OSC32KCTRL) Clock selection */
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#define REG_OSC32KCTRL_XOSC32K (*(RwReg *)0x40001014U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
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#define REG_OSC32KCTRL_OSC32K (*(RwReg *)0x40001018U) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */
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#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000101CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
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#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6
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#endif /* _SAML21_OSC32KCTRL_INSTANCE_ */
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