/** * \file * * \brief Instance description for OSC32KCTRL * * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. * * \asf_license_start * * \page License * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. The name of Atmel may not be used to endorse or promote products derived * from this software without specific prior written permission. * * 4. This software may only be redistributed and used in connection with an * Atmel microcontroller product. * * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * \asf_license_stop * */ /* * Support and FAQ: visit Atmel Support */ #ifndef _SAML21_OSC32KCTRL_INSTANCE_ #define _SAML21_OSC32KCTRL_INSTANCE_ /* ========== Register definition for OSC32KCTRL peripheral ========== */ #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) #define REG_OSC32KCTRL_INTENCLR (0x40001000U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ #define REG_OSC32KCTRL_INTENSET (0x40001004U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ #define REG_OSC32KCTRL_INTFLAG (0x40001008U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ #define REG_OSC32KCTRL_STATUS (0x4000100CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */ #define REG_OSC32KCTRL_RTCCTRL (0x40001010U) /**< \brief (OSC32KCTRL) Clock selection */ #define REG_OSC32KCTRL_XOSC32K (0x40001014U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ #define REG_OSC32KCTRL_OSC32K (0x40001018U) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */ #define REG_OSC32KCTRL_OSCULP32K (0x4000101CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ #else #define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001000U) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */ #define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001004U) /**< \brief (OSC32KCTRL) Interrupt Enable Set */ #define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001008U) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */ #define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000100CU) /**< \brief (OSC32KCTRL) Power and Clocks Status */ #define REG_OSC32KCTRL_RTCCTRL (*(RwReg *)0x40001010U) /**< \brief (OSC32KCTRL) Clock selection */ #define REG_OSC32KCTRL_XOSC32K (*(RwReg *)0x40001014U) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ #define REG_OSC32KCTRL_OSC32K (*(RwReg *)0x40001018U) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */ #define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000101CU) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ /* ========== Instance parameters for OSC32KCTRL peripheral ========== */ #define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6 #endif /* _SAML21_OSC32KCTRL_INSTANCE_ */