2016-08-15 22:41:07 +02:00
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# Define the CPU family so we can differentiate between them in the code
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2019-08-29 17:41:49 +02:00
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CFLAGS += -DCPU_FAM_$(call uppercase_and_underscore,$(CPU_FAM))
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2016-02-08 18:22:11 +01:00
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2020-02-06 19:52:05 +01:00
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# Generate ASF compatible model definition
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CFLAGS += -D__$(call uppercase_and_underscore,$(CPU_MODEL))__
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2017-10-13 18:45:35 +02:00
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# Set ROM and RAM lengths according to CPU model
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2019-03-23 22:11:15 +01:00
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ifneq (,$(filter samd21g18a samd21j18a saml21j18b saml21j18a samr21e18a \
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samr21g18a samr30g18a samr34j18b,$(CPU_MODEL)))
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2017-10-13 18:45:35 +02:00
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ROM_LEN ?= 0x40000
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RAM_LEN ?= 0x8000
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endif
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2019-01-21 17:06:58 +01:00
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ifneq (,$(filter saml10e16a saml11e16a,$(CPU_MODEL)))
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ROM_LEN ?= 64K
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RAM_LEN ?= 16K
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endif
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2019-03-12 13:57:27 +01:00
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ifneq (,$(filter samd51j20a same54p20a,$(CPU_MODEL)))
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ROM_LEN ?= 1024K
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RAM_LEN ?= 256K
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endif
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2017-10-13 18:45:35 +02:00
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ROM_START_ADDR ?= 0x00000000
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RAM_START_ADDR ?= 0x20000000
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2016-02-08 18:22:11 +01:00
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# this CPU implementation doesn't use CMSIS initialization
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2019-08-27 16:06:41 +02:00
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CFLAGS += -DDONT_USE_CMSIS_INIT
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CFLAGS += -DDONT_USE_PREDEFINED_CORE_HANDLERS
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CFLAGS += -DDONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
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2016-02-08 18:22:11 +01:00
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2017-10-13 18:45:35 +02:00
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# For Cortex-M cpu we use the common cortexm.ld linker script
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LINKER_SCRIPT ?= cortexm.ld
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2016-12-15 11:39:19 +01:00
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2019-12-20 21:19:44 +01:00
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# define sam0 specific pseudomodules
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PSEUDOMODULES += sam0_periph_uart_hw_fc
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2019-08-27 16:06:41 +02:00
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INCLUDES += -I$(RIOTCPU)/sam0_common/include
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