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136 lines
9.2 KiB
C
136 lines
9.2 KiB
C
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/***************************************************************************//**
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* @file
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* @brief EFM32HG_MTB register and bit field definitions
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*******************************************************************************
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* # License
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* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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******************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(__ICCARM__)
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#pragma system_include /* Treat file as system include file. */
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* Treat file as system include file. */
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#endif
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/***************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @defgroup EFM32HG_MTB
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* @{
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* @brief EFM32HG_MTB Register Declaration
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******************************************************************************/
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typedef struct {
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__IOM uint32_t POSITION; /**< MTB Trace Position Register. */
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__IOM uint32_t MASTER; /**< MTB Trace Control Register */
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__IOM uint32_t FLOW; /**< MTB Trace Flow Register */
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__IOM uint32_t BASE; /**< MTB Trace Base Register */
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} MTB_TypeDef; /**< MTB Register Declaration *//** @} */
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/***************************************************************************//**
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* @defgroup EFM32HG_MTB_BitFields
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* @{
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******************************************************************************/
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/* Bit fields for MTB POSITION */
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#define _MTB_POSITION_RESETVALUE 0x00000000UL /**< Default value for MTB_POSITION */
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#define _MTB_POSITION_MASK 0xFFFFFFFCUL /**< Mask for MTB_POSITION */
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#define MTB_POSITION_WRAP (0x1UL << 2) /**< Trace wrap bit. */
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#define _MTB_POSITION_WRAP_SHIFT 2 /**< Shift value for MTB_WRAP */
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#define _MTB_POSITION_WRAP_MASK 0x4UL /**< Bit mask for MTB_WRAP */
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#define _MTB_POSITION_WRAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_POSITION */
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#define MTB_POSITION_WRAP_DEFAULT (_MTB_POSITION_WRAP_DEFAULT << 2) /**< Shifted mode DEFAULT for MTB_POSITION */
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#define _MTB_POSITION_POINTER_SHIFT 3 /**< Shift value for MTB_POINTER */
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#define _MTB_POSITION_POINTER_MASK 0xFFFFFFF8UL /**< Bit mask for MTB_POINTER */
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#define _MTB_POSITION_POINTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_POSITION */
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#define MTB_POSITION_POINTER_DEFAULT (_MTB_POSITION_POINTER_DEFAULT << 3) /**< Shifted mode DEFAULT for MTB_POSITION */
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/* Bit fields for MTB MASTER */
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#define _MTB_MASTER_RESETVALUE 0x00000000UL /**< Default value for MTB_MASTER */
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#define _MTB_MASTER_MASK 0x8000027FUL /**< Mask for MTB_MASTER */
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#define _MTB_MASTER_MASK_SHIFT 0 /**< Shift value for MTB_MASK */
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#define _MTB_MASTER_MASK_MASK 0x1FUL /**< Bit mask for MTB_MASK */
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#define _MTB_MASTER_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */
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#define MTB_MASTER_MASK_DEFAULT (_MTB_MASTER_MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for MTB_MASTER */
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#define MTB_MASTER_TSTARTEN (0x1UL << 5) /**< Trace start input enable. */
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#define _MTB_MASTER_TSTARTEN_SHIFT 5 /**< Shift value for MTB_TSTARTEN */
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#define _MTB_MASTER_TSTARTEN_MASK 0x20UL /**< Bit mask for MTB_TSTARTEN */
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#define _MTB_MASTER_TSTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */
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#define MTB_MASTER_TSTARTEN_DEFAULT (_MTB_MASTER_TSTARTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MTB_MASTER */
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#define MTB_MASTER_TSTOPEN (0x1UL << 6) /**< Trace stop input enable. */
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#define _MTB_MASTER_TSTOPEN_SHIFT 6 /**< Shift value for MTB_TSTOPEN */
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#define _MTB_MASTER_TSTOPEN_MASK 0x40UL /**< Bit mask for MTB_TSTOPEN */
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#define _MTB_MASTER_TSTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */
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#define MTB_MASTER_TSTOPEN_DEFAULT (_MTB_MASTER_TSTOPEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MTB_MASTER */
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#define MTB_MASTER_HALTREQ (0x1UL << 9) /**< Halt request bit. */
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#define _MTB_MASTER_HALTREQ_SHIFT 9 /**< Shift value for MTB_HALTREQ */
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#define _MTB_MASTER_HALTREQ_MASK 0x200UL /**< Bit mask for MTB_HALTREQ */
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#define _MTB_MASTER_HALTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */
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#define MTB_MASTER_HALTREQ_DEFAULT (_MTB_MASTER_HALTREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for MTB_MASTER */
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#define MTB_MASTER_EN (0x1UL << 31) /**< Main trace enable bit. */
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#define _MTB_MASTER_EN_SHIFT 31 /**< Shift value for MTB_EN */
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#define _MTB_MASTER_EN_MASK 0x80000000UL /**< Bit mask for MTB_EN */
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#define _MTB_MASTER_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_MASTER */
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#define MTB_MASTER_EN_DEFAULT (_MTB_MASTER_EN_DEFAULT << 31) /**< Shifted mode DEFAULT for MTB_MASTER */
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/* Bit fields for MTB FLOW */
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#define _MTB_FLOW_RESETVALUE 0x00000000UL /**< Default value for MTB_FLOW */
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#define _MTB_FLOW_MASK 0xFFFFFFFBUL /**< Mask for MTB_FLOW */
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#define MTB_FLOW_AUTOSTOP (0x1UL << 0) /**< AUTOSTOP enable. */
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#define _MTB_FLOW_AUTOSTOP_SHIFT 0 /**< Shift value for MTB_AUTOSTOP */
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#define _MTB_FLOW_AUTOSTOP_MASK 0x1UL /**< Bit mask for MTB_AUTOSTOP */
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#define _MTB_FLOW_AUTOSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_FLOW */
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#define MTB_FLOW_AUTOSTOP_DEFAULT (_MTB_FLOW_AUTOSTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for MTB_FLOW */
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#define MTB_FLOW_AUTOHALT (0x1UL << 1) /**< AUTOHALT enable. */
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#define _MTB_FLOW_AUTOHALT_SHIFT 1 /**< Shift value for MTB_AUTOHALT */
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#define _MTB_FLOW_AUTOHALT_MASK 0x2UL /**< Bit mask for MTB_AUTOHALT */
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#define _MTB_FLOW_AUTOHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_FLOW */
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#define MTB_FLOW_AUTOHALT_DEFAULT (_MTB_FLOW_AUTOHALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MTB_FLOW */
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#define _MTB_FLOW_WATERMARK_SHIFT 3 /**< Shift value for MTB_WATERMARK */
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#define _MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8UL /**< Bit mask for MTB_WATERMARK */
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#define _MTB_FLOW_WATERMARK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MTB_FLOW */
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#define MTB_FLOW_WATERMARK_DEFAULT (_MTB_FLOW_WATERMARK_DEFAULT << 3) /**< Shifted mode DEFAULT for MTB_FLOW */
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/* Bit fields for MTB BASE */
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#define _MTB_BASE_RESETVALUE 0x20000000UL /**< Default value for MTB_BASE */
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#define _MTB_BASE_MASK 0xFFFFFFFFUL /**< Mask for MTB_BASE */
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#define _MTB_BASE_BASE_SHIFT 0 /**< Shift value for MTB_BASE */
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#define _MTB_BASE_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MTB_BASE */
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#define _MTB_BASE_BASE_DEFAULT 0x20000000UL /**< Mode DEFAULT for MTB_BASE */
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#define MTB_BASE_BASE_DEFAULT (_MTB_BASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MTB_BASE */
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/** @} End of group EFM32HG_MTB */
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/** @} End of group Parts */
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#ifdef __cplusplus
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}
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#endif
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