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45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
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/*
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* hwtimer_cpu.c - architecture dependent hardware timer functionality
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*/
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#include <stdint.h>
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#include "mc1322x.h"
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/* TODO: do scaling voodoo */
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#define COUNT_MODE 1 /* use rising edge of primary source */
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#define PRIME_SRC 0xf /* Perip. clock with 128 prescale (for 24Mhz = 187500Hz)*/
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#define SEC_SRC 0 /* don't need this */
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#define ONCE 0 /* keep counting */
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#define LEN 0 /* continue counting */
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#define DIR 0 /* count up */
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#define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */
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#define OUT_MODE 0 /* OFLAG is asserted while counter is active */
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void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) {
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/* Reset the timer */
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TMR_ENBL = 0;
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/* Clear status */
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TMR0_SCTRL = 0;
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/* disable interrupt */
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TMR0_CSCTRL =0x0000;
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/* Reload/initialize to zero */
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TMR0_LOAD = 0;
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/* disable comparison */
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TMR0_COMP_UP = 0;
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TMR0_CMPLD1 = 0;
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/* set counter to zero */
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TMR0_CNTR = 0;
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TMR0_CTRL = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
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TMR_ENBL = 0xf; /* enable all the timers --- why not? */
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}
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