mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
* added header and preliminary hwtimer code for mc1322x
* renamed start to startup
This commit is contained in:
Oliver Hahm
parent
5ae8c46c88
commit
2177b130d7
44
cpu/mc1322x/hwtimer_cpu.c
Normal file
44
cpu/mc1322x/hwtimer_cpu.c
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@ -0,0 +1,44 @@
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/*
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* hwtimer_cpu.c - architecture dependent hardware timer functionality
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*/
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#include <stdint.h>
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#include "mc1322x.h"
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/* TODO: do scaling voodoo */
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#define COUNT_MODE 1 /* use rising edge of primary source */
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#define PRIME_SRC 0xf /* Perip. clock with 128 prescale (for 24Mhz = 187500Hz)*/
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#define SEC_SRC 0 /* don't need this */
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#define ONCE 0 /* keep counting */
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#define LEN 0 /* continue counting */
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#define DIR 0 /* count up */
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#define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */
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#define OUT_MODE 0 /* OFLAG is asserted while counter is active */
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void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) {
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/* Reset the timer */
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TMR_ENBL = 0;
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/* Clear status */
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TMR0_SCTRL = 0;
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/* disable interrupt */
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TMR0_CSCTRL =0x0000;
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/* Reload/initialize to zero */
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TMR0_LOAD = 0;
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/* disable comparison */
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TMR0_COMP_UP = 0;
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TMR0_CMPLD1 = 0;
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/* set counter to zero */
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TMR0_CNTR = 0;
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TMR0_CTRL = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
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TMR_ENBL = 0xf; /* enable all the timers --- why not? */
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}
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@ -10,6 +10,7 @@
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#define CPU_H
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#include <stdint.h>
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#include "mc1322x.h"
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extern uintptr_t __stack_start; ///< end of user stack memory space
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210
cpu/mc1322x/include/mc1322x.h
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210
cpu/mc1322x/include/mc1322x.h
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@ -0,0 +1,210 @@
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/*
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* mc1322x.h - mc1322x specific definitions
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* Copyright (C) 2013 Oliver Hahm <oliver.hahm@inria.fr>
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*
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* This source code is licensed under the GNU General Public License,
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* Version 3. See the file LICENSE for more details.
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*
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* This file is part of RIOT.
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*/
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#ifndef MC1322X_H
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#define MC1322X_H
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#define F_CPU (24000000) ///< CPU target speed in Hz
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/* Timer registers are all 16-bit wide with 16-bit access only */
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#define TMR_OFFSET (0x20)
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#define TMR_BASE (0x80007000)
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#define TMR0_BASE (TMR_BASE)
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#define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
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#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
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#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
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/* Structure-based register definitions */
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/* Example use:
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TMR2->CTRL = 0x1234;
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TMR2->CTRLbits = (struct TMR_CTRL) {
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.DIR = 1,
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.OUTPUT_MODE = 2,
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};
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TMR2->CTRLbits.PRIMARY_CNT_SOURCE = 3;
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*/
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struct TMR_struct {
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uint16_t COMP1;
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uint16_t COMP2;
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uint16_t CAPT;
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uint16_t LOAD;
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uint16_t HOLD;
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uint16_t CNTR;
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union {
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uint16_t CTRL;
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struct TMR_CTRL {
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uint16_t OUTPUT_MODE:3;
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uint16_t CO_INIT:1;
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uint16_t DIR:1;
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uint16_t LENGTH:1;
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uint16_t ONCE:1;
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uint16_t SECONDARY_CNT_SOURCE:2;
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uint16_t PRIMARY_CNT_SOURCE:4;
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uint16_t COUNT_MODE:3;
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} CTRLbits;
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};
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union {
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uint16_t SCTRL;
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struct TMR_SCTRL {
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uint16_t OEN:1;
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uint16_t OPS:1;
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uint16_t FORCE:1;
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uint16_t VAL:1;
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uint16_t EEOF:1;
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uint16_t MSTR:1;
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uint16_t CAPTURE_MODE:2;
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uint16_t INPUT:1;
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uint16_t IPS:1;
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uint16_t IEFIE:1;
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uint16_t IEF:1;
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uint16_t TOFIE:1;
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uint16_t TOF:1;
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uint16_t TCFIE:1;
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uint16_t TCF:1;
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} SCTRLbits;
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};
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uint16_t CMPLD1;
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uint16_t CMPLD2;
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union {
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uint16_t CSCTRL;
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struct TMR_CSCTRL {
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uint16_t CL1:2;
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uint16_t CL2:2;
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uint16_t TCF1:1;
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uint16_t TCF2:1;
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uint16_t TCF1EN:1;
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uint16_t TCF2EN:1;
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uint16_t :5;
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uint16_t FILT_EN:1;
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uint16_t DBG_EN:2;
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} CSCTRLbits;
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};
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uint16_t reserved[4];
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union {
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uint16_t ENBL;
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struct TMR_ENBL {
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union {
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struct {
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uint16_t ENBL:4;
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};
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struct {
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uint16_t ENBL3:1;
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uint16_t ENBL2:1;
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uint16_t ENBL1:1;
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uint16_t ENBL0:1;
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};
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};
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uint16_t :12;
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} ENBLbits;
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};
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};
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static volatile struct TMR_struct * const TMR0 = (void *) (TMR0_BASE);
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static volatile struct TMR_struct * const TMR1 = (void *) (TMR1_BASE);
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static volatile struct TMR_struct * const TMR2 = (void *) (TMR2_BASE);
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static volatile struct TMR_struct * const TMR3 = (void *) (TMR3_BASE);
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/* Get timer pointer from timer number */
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#define TMR_ADDR(x) (*(volatile struct TMR_struct *)(((uint32_t)(x) * TMR_OFFSET) + TMR_BASE))
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/* Get timer number from the timer pointer. */
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#define TMR_NUM(x) (((uint32_t)(x) - TMR_BASE) / TMR_OFFSET)
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/* Used to compute which enable bit to set for a particular timer, e.g.
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TMR0.ENBL |= TMR_ENABLE_BIT(TMR2);
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Helpful when you're using macros to define timers
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*/
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#define TMR_ENABLE_BIT(x) (1 << TMR_NUM(x))
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#define TMR0_PIN GPIO_08
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#define TMR1_PIN GPIO_09
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#define TMR2_PIN GPIO_10
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#define TMR3_PIN GPIO_11
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#define TMR_REGOFF_COMP1 (0x0)
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#define TMR_REGOFF_COMP2 (0x2)
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#define TMR_REGOFF_CAPT (0x4)
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#define TMR_REGOFF_LOAD (0x6)
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#define TMR_REGOFF_HOLD (0x8)
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#define TMR_REGOFF_CNTR (0xa)
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#define TMR_REGOFF_CTRL (0xc)
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#define TMR_REGOFF_SCTRL (0xe)
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#define TMR_REGOFF_CMPLD1 (0x10)
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#define TMR_REGOFF_CMPLD2 (0x12)
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#define TMR_REGOFF_CSCTRL (0x14)
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#define TMR_REGOFF_ENBL (0x1e)
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/* one enable register to rule them all */
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#define TMR_ENBL (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_ENBL))
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/* Timer 0 registers */
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#define TMR0_COMP1 (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP1))
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#define TMR0_COMP_UP TMR0_COMP1
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#define TMR0_COMP2 (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP2))
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#define TMR0_COMP_DOWN TMR0_COMP2
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#define TMR0_CAPT (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CAPT))
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#define TMR0_LOAD (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_LOAD))
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#define TMR0_HOLD (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_HOLD))
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#define TMR0_CNTR (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CNTR))
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#define TMR0_CTRL (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CTRL))
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#define TMR0_SCTRL (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_SCTRL))
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#define TMR0_CMPLD1 (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD1))
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#define TMR0_CMPLD2 (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD2))
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#define TMR0_CSCTRL (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 1 registers */
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#define TMR1_COMP1 (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP1))
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#define TMR1_COMP_UP TMR1_COMP1
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#define TMR1_COMP2 (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP2))
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#define TMR1_COMP_DOWN TMR1_COMP2
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#define TMR1_CAPT (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CAPT))
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#define TMR1_LOAD (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_LOAD))
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#define TMR1_HOLD (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_HOLD))
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#define TMR1_CNTR (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CNTR))
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#define TMR1_CTRL (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CTRL))
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#define TMR1_SCTRL (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_SCTRL))
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#define TMR1_CMPLD1 (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD1))
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#define TMR1_CMPLD2 (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD2))
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#define TMR1_CSCTRL (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 2 registers */
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#define TMR2_COMP1 (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP1))
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#define TMR2_COMP_UP TMR2_COMP1
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#define TMR2_COMP2 (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP2))
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#define TMR2_COMP_DOWN TMR2_COMP2
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#define TMR2_CAPT (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CAPT))
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#define TMR2_LOAD (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_LOAD))
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#define TMR2_HOLD (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_HOLD))
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#define TMR2_CNTR (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CNTR))
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#define TMR2_CTRL (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CTRL))
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#define TMR2_SCTRL (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_SCTRL))
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#define TMR2_CMPLD1 (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD1))
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#define TMR2_CMPLD2 (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD2))
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#define TMR2_CSCTRL (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 3 registers */
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#define TMR3_COMP1 (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP1))
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#define TMR3_COMP_UP TMR3_COMP1
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#define TMR3_COMP2 (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP2))
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#define TMR3_COMP_DOWN TMR3_COMP2
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#define TMR3_CAPT (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CAPT))
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#define TMR3_LOAD (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_LOAD))
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#define TMR3_HOLD (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_HOLD))
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#define TMR3_CNTR (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CNTR))
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#define TMR3_CTRL (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CTRL))
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#define TMR3_SCTRL (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_SCTRL))
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#define TMR3_CMPLD1 (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD1))
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#define TMR3_CMPLD2 (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD2))
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#define TMR3_CSCTRL (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CSCTRL))
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#define TMR(num, reg) CAT2(TMR,num,_##reg)
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#endif /* MC1322X_H */
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@ -2,7 +2,7 @@
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OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
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"elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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ENTRY(_startup)
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MEMORY
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{
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@ -24,7 +24,7 @@ HEAP_SIZE = 4096;
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PROVIDE (__executable_start = 0x00400000); . = 0x00400000;
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.text :
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{
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*(.start)
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*(.startup)
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*(.irq)
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*(.text .stub .text.* .gnu.linkonce.t.*)
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/* .gnu.warning sections are handled specially by elf32.em. */
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
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* to the MC1322x project (http://mc1322x.devl.org) and Contiki.
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* to the MC1322x project (http:/*mc1322x.devl.org) and Contiki.
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*
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* All rights reserved.
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*
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@ -58,38 +58,38 @@ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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// Stack Sizes
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/* Stack Sizes */
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.set UND_STACK_SIZE, 0x00000004
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.set ABT_STACK_SIZE, 0x00000004
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.set FIQ_STACK_SIZE, 0x00000004
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.set IRQ_STACK_SIZE, 0X00000080
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.set SVC_STACK_SIZE, 0x00000004
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// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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.set MODE_USR, 0x10 // User Mode
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.set MODE_FIQ, 0x11 // FIQ Mode
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.set MODE_IRQ, 0x12 // IRQ Mode
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.set MODE_SVC, 0x13 // Supervisor Mode
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.set MODE_ABT, 0x17 // Abort Mode
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.set MODE_UND, 0x1B // Undefined Mode
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.set MODE_SYS, 0x1F // System Mode
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/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
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.set MODE_USR, 0x10 /* User Mode */
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.set MODE_FIQ, 0x11 /* FIQ Mode */
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.set MODE_IRQ, 0x12 /* IRQ Mode */
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.set MODE_SVC, 0x13 /* Supervisor Mode */
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.set MODE_ABT, 0x17 /* Abort Mode */
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.set MODE_UND, 0x1B /* Undefined Mode */
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.set MODE_SYS, 0x1F /* System Mode */
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.equ I_BIT, 0x80 // when I bit is set, IRQ is disabled
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.equ F_BIT, 0x40 // when F bit is set, FIQ is disabled
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.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
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.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
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.section .start
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.set _rom_data_init, 0x108d0
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.global _start
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_start:
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b _begin // reset - _start
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ldr pc,_undf // undefined
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ldr pc,_swi // SWI
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ldr pc,_pabt // program abort
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ldr pc,_dabt // data abort
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nop // reserved
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ldr pc,_irq // IRQ
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ldr pc,_fiq // FIQ
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_startup:
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b _begin /* reset - _start */
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ldr pc,_undf /* undefined */
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ldr pc,_swi /* SWI */
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ldr pc,_pabt /* program abort */
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ldr pc,_dabt /* data abort */
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nop /* reserved */
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ldr pc,_irq /* IRQ */
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ldr pc,_fiq /* FIQ */
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/* these vectors are used for rom patching */
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.org 0x20
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@ -163,20 +163,20 @@ clbss_l:
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b main
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_undf: .word __undf // undefined
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_swi: .word __swi // SWI
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_pabt: .word __pabt // program abort
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_dabt: .word __dabt // data abort
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_irq: .word irq // IRQ
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_fiq: .word __fiq // FIQ
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_undf: .word __undf /* undefined */
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_swi: .word __swi /* SWI */
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_pabt: .word __pabt /* program abort */
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_dabt: .word __dabt /* data abort */
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_irq: .word irq /* IRQ */
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_fiq: .word __fiq /* FIQ */
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__undf: b . // undefined
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__swi: b . // SWI
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__pabt: b . // program abort
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__dabt: b . // data abort
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__undf: b . /* undefined */
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__swi: b . /* SWI */
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__pabt: b . /* program abort */
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__dabt: b . /* data abort */
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/* IRQ handler set in isr.c */
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//__irq: b . // IRQ
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__fiq: b . // FIQ
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/*__irq: b . // IRQ */
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__fiq: b . /* FIQ */
|
||||
|
||||
/*
|
||||
* These are defined in the board-specific linker script.
|
||||
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Reference in New Issue
Block a user