2019-10-08 09:05:11 +02:00
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CPU_ARCH = cortex-m4f
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2019-10-08 15:26:11 +02:00
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CPU_FAM = nrf52
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2016-02-04 15:30:06 +01:00
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2019-05-13 16:08:54 +02:00
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# Slot size is determined by "((total_flash_size - RIOTBOOT_LEN) / 2)".
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# If RIOTBOOT_LEN uses an uneven number of flashpages, the remainder of the
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# flash cannot be divided by two slots while staying FLASHPAGE_SIZE aligned.
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RIOTBOOT_LEN ?= 0x2000
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2017-07-03 14:27:22 +02:00
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# Export internal ROM alignment and slot sizes for bootloader support
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2018-02-06 16:41:48 +01:00
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export MCUBOOT_IMAGE_ALIGN = 8
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export MCUBOOT_SLOT0_SIZE = 0x8000
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export MCUBOOT_SLOT1_SIZE = 0x3C000
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export MCUBOOT_SLOT2_SIZE = 0x3C000
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2017-07-03 14:27:22 +02:00
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2019-03-07 14:27:45 +01:00
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# Set ROM and RAM lengths according to CPU model
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ifneq (,$(filter nrf52832xxaa,$(CPU_MODEL)))
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ROM_LEN ?= 0x80000
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RAM_LEN ?= 0x10000
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endif
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ifneq (,$(filter nrf52840xxaa,$(CPU_MODEL)))
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ROM_LEN ?= 0x100000
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RAM_LEN ?= 0x40000
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endif
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ROM_START_ADDR ?= 0x00000000
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RAM_START_ADDR ?= 0x20000000
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LINKER_SCRIPT ?= cortexm.ld
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2016-02-07 12:55:42 +01:00
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include $(RIOTCPU)/nrf5x_common/Makefile.include
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2016-01-27 10:47:12 +01:00
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include $(RIOTMAKE)/arch/cortexm.inc.mk
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