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RIOT/boards/hifive1/Makefile.features

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board/hifive1: add RISC-V board HiFive1 Add new RISC-V board HiFive1 from SiFive based on FE310 CPU
2018-04-16 19:07:04 +02:00
# Put defined MCU peripherals here (in alphabetical order)
make: Introduce new feature flag periph_gpio_irq
2018-08-26 09:20:56 +02:00
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit build: fixed missing syscall and cpuid failures Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph build: fixed whitespace error build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY doc: fixed doxygen warnings Addressed Doxygen warnings in source file comments doc: more doxygen fixes doc: even more doxygen fixes doc: more changes build: fix pedantic and rdci_simple build failures make: exclude lua
2018-04-16 22:35:32 +02:00
#FEATURES_PROVIDED += periph_pwm
board/hifive1: add RISC-V board HiFive1 Add new RISC-V board HiFive1 from SiFive based on FE310 CPU
2018-04-16 19:07:04 +02:00
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
#FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = risc_v
boards/hifive1: include cpu/fe310 features The board should process its CPU features. This has the consequence to make 'periph_pm' visible to the board. I also removed the duplicate FEATURES_PROVIDED from the board defined in the cpu.
2018-09-27 18:21:59 +02:00
include $(RIOTCPU)/fe310/Makefile.features
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