RIOT/boards/hifive1/Makefile.features

# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
#FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
#FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

ifneq (,$(filter periph_rtc,$(FEATURES_REQUIRED)))
  FEATURES_REQUIRED += periph_rtt
endif

# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = risc_v
board/hifive1: add RISC-V board HiFive1 Add new RISC-V board HiFive1 from SiFive based on FE310 CPU 2018-04-16 19:07:04 +02:00			`# Put defined MCU peripherals here (in alphabetical order)`
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit build: fixed missing syscall and cpuid failures Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph build: fixed whitespace error build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY doc: fixed doxygen warnings Addressed Doxygen warnings in source file comments doc: more doxygen fixes doc: even more doxygen fixes doc: more changes build: fix pedantic and rdci_simple build failures make: exclude lua 2018-04-16 22:35:32 +02:00			`FEATURES_PROVIDED += periph_cpuid`
board/hifive1: add RISC-V board HiFive1 Add new RISC-V board HiFive1 from SiFive based on FE310 CPU 2018-04-16 19:07:04 +02:00			`FEATURES_PROVIDED += periph_gpio`
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit build: fixed missing syscall and cpuid failures Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph build: fixed whitespace error build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY doc: fixed doxygen warnings Addressed Doxygen warnings in source file comments doc: more doxygen fixes doc: even more doxygen fixes doc: more changes build: fix pedantic and rdci_simple build failures make: exclude lua 2018-04-16 22:35:32 +02:00			`#FEATURES_PROVIDED += periph_pwm`
board/hifive1: add RISC-V board HiFive1 Add new RISC-V board HiFive1 from SiFive based on FE310 CPU 2018-04-16 19:07:04 +02:00			`FEATURES_PROVIDED += periph_rtc`
			`FEATURES_PROVIDED += periph_rtt`
			`#FEATURES_PROVIDED += periph_spi`
			`FEATURES_PROVIDED += periph_timer`
			`FEATURES_PROVIDED += periph_uart`

			`ifneq (,$(filter periph_rtc,$(FEATURES_REQUIRED)))`
			`FEATURES_REQUIRED += periph_rtt`
			`endif`

			`# The board MPU family (used for grouping by the CI system)`
			`FEATURES_MCU_GROUP = risc_v`