RIOT-OS/RIOT
RIOT-OS/RIOT
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RIOT/cpu/riscv_common/start.S

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cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
/*
* Copyright (C) 2017 JP Bonn, Ken Rabold
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
cpu/riscv_common: Jump to rom start on boot With this the riscv start code jumps to the ROM start on boot when the ROM area doesn't start at address 0x0.
2021-02-17 11:36:19 +01:00
#include "vendor/riscv_csr.h"
.section .init
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
.globl _start
.type _start,@function
_start:
.cfi_startproc
.cfi_undefined ra
.option push
.option norelax
cpu/riscv_common: Jump to rom start on boot With this the riscv start code jumps to the ROM start on boot when the ROM area doesn't start at address 0x0.
2021-02-17 11:36:19 +01:00
csrc CSR_MSTATUS, MSTATUS_MIE
riscv: Simplify reset trampoline By loading the absolute address of _start_real we can unconditionally jump to it regardless if the PC is somewhere at 0x0 or at ROM_START_ADDR
2021-09-22 10:37:23 +02:00
lui a0, %hi(_start_real)
riscv: Reduce reset trampoline code size by 2 bytes `addi` with 20 bit immediate does not have a compressed representation, so using `jalr` with immediate offset uncompressed is smaller than using `addi`+`c.jr`
2022-12-08 13:20:14 +01:00
jalr x0, a0, %lo(_start_real)
cpu/riscv_common: Jump to rom start on boot With this the riscv start code jumps to the ROM start on boot when the ROM area doesn't start at address 0x0.
2021-02-17 11:36:19 +01:00
_start_real:
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
la gp, __global_pointer$
.option pop
la sp, _sp
cpu/riscv_common: add puf_sram feature
2022-02-16 10:59:14 +01:00
#ifdef MODULE_PUF_SRAM
/* PUF */
call riscv_puf_sram_init
#endif
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
/* Load data section */
la a0, _data_lma
la a1, _data
la a2, _edata
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
cpu/riscv_common: add bss end to clear memory
2022-02-16 10:52:09 +01:00
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
/* Clear bss section */
la a0, __bss_start
cpu/riscv_common: add bss end to clear memory
2022-02-16 10:52:09 +01:00
la a1, __bss_end
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
bgeu a0, a1, 2f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
2:
/* Call global constructors */
call __libc_init_array
cpu/riscv_common: call cpu_init()
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/* Initialize CPU, board and start kernel */
call cpu_init
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
2018-04-16 19:03:33 +02:00
call board_init
call kernel_init
/* Loop forever (should never get here) */
1:
j 1b
.cfi_endproc
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