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RIOT/cpu/stm32/Makefile.features

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cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
include $(RIOTCPU)/stm32/stm32_info.mk
cpu/stm32: do not build bootloader for mp1 The stm32mp1 family has no flash. The firmware is loaded directly in RAM by stlink programmer or by Cortex-A7 bootloader/OS. Thus bootloader is useless for this family, disable it. Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-08-03 00:31:59 +02:00
ifneq (mp1,$(CPU_FAM))
FEATURES_PROVIDED += bootloader_stm32
cpu/stm32: disable periph_wdt for mp1 family In STM32MP1 family, independant watchdogs (IWDG1 and IWDG2) are dedicated to the MPU (Cortex-A7). Thus simply disable the feature for STM32MP1 family. Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-05 01:06:10 +01:00
FEATURES_PROVIDED += periph_wdt
cpu/stm32: do not build bootloader for mp1 The stm32mp1 family has no flash. The firmware is loaded directly in RAM by stlink programmer or by Cortex-A7 bootloader/OS. Thus bootloader is useless for this family, disable it. Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-08-03 00:31:59 +02:00
endif
cpu/stm32: fix issue with cpu feature name
2020-05-30 18:59:01 +02:00
FEATURES_PROVIDED += cpu_stm32$(CPU_FAM)
cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
cpu/stm32: implement periph_timer_periodic Seems like the Interrupt flag for a Capture/Compare channel gets set when - the CC-value is reached - the timer resets before the CC value is reached. We only want the first event and ignore the second one. Unfortunately I did not find a way to disable the second event type, so it is filtered in software. That is we need to - ignore the CC-interrupts when the COUNT register register is reset - ignore the CC-interrupts > TOP value/ARR (auto-reload register)
2020-06-29 22:15:48 +02:00
FEATURES_PROVIDED += periph_timer_periodic
cpu: add periph_rtt_overflow feature The RTT overflow callback is not available on all RTT implementations. This means it is either a no-op or `rtt_set_overflow_cb()` is a no-op or it will overwrite the alarm set with `rtt_set_alarm()`. This adds a feature to indicate that proper overflow reporting is available.
2021-01-13 20:48:29 +01:00
FEATURES_PROVIDED += periph_rtt_overflow
cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
FEATURES_PROVIDED += periph_uart_modecfg
cpu/stm32: add non blocking uart Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2020-06-10 15:44:58 +02:00
FEATURES_PROVIDED += periph_uart_nonblocking
cpu/stm32: Implement gpio_ll for STM32F1 This provides basic GPIO LL support. IRQ support will be added as follow up.
2023-03-17 14:34:44 +01:00
FEATURES_PROVIDED += periph_gpio_ll
cpu/stm32: Implement GPIO LL IRQ support for STM32F1
2023-03-20 14:07:14 +01:00
FEATURES_PROVIDED += periph_gpio_ll_irq
FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_low
cpu/stm32: Implement periph/gpio_ll{,_irq} except for STM32F1 Co-authored-by: Gunar Schorcht <gunar@schorcht.net> Co-authored-by: Alexandre Abadie <alexandre.abadie@inria.fr>
2021-08-27 22:59:43 +02:00
cpu/stm32: add initial support for stm32u5 family
2021-12-15 15:53:53 +01:00
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl))
cpu/stm32: enable flashpage feature for stm32f031k6
2020-07-15 11:51:44 +02:00
FEATURES_PROVIDED += periph_flashpage
periph/flashpage: Add _in_address_space feature
2022-03-17 19:45:54 +01:00
FEATURES_PROVIDED += periph_flashpage_in_address_space
stm32: Adapt to flashpage/flashpage_pagewise API
2020-11-09 16:45:22 +01:00
FEATURES_PROVIDED += periph_flashpage_pagewise
cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
endif
cpu/stm32: add initial support for stm32u5 family
2021-12-15 15:53:53 +01:00
ifneq (,$(filter $(CPU_FAM),f0 f2 f3 f4 f7 l0 l1 l4 l5 u5 wb wl))
cpu/stm32: add rtc_mem
2021-09-03 11:15:17 +02:00
CPU_MODELS_WITHOUT_RTC_BKPR += stm32f030% stm32f070%
ifeq (,$(filter $(CPU_MODELS_WITHOUT_RTC_BKPR),$(CPU_MODEL)))
FEATURES_PROVIDED += periph_rtc_mem
endif
endif
cpu/{cortexm_common, stm32}: add support for backup RAM
2021-09-16 09:58:37 +02:00
STM32_WITH_BKPRAM = stm32f205% stm32f207% stm32f215% stm32f217% \
stm32f405% stm32f407% stm32f415% stm32f417% \
stm32f427% stm32f429% stm32f437% stm32f439% \
stm32f446% stm32f469% stm32f479% \
stm32f7% \
stm32u5%
ifneq (,$(filter $(STM32_WITH_BKPRAM),$(CPU_MODEL)))
FEATURES_PROVIDED += backup_ram
endif
cpu/stm32: add VBAT for stm32
2021-10-12 13:16:57 +02:00
STM32_WITH_VBAT = stm32f031% stm32f038% stm32f042% stm32f048% \
stm32f051% stm32f058% stm32f071% stm32f072% \
stm32f078% stm32f091% stm32f098% \
stm32f2% \
stm32f3% \
stm32f4% \
stm32f7% \
stm32g0% \
stm32g4% stm32gbk1cb \
stm32l4% \
stm32l5% \
stm32u5% \
stm32wb% \
stm32wl%
ifneq (,$(filter $(STM32_WITH_VBAT),$(CPU_MODEL)))
FEATURES_PROVIDED += periph_vbat
endif
stm32f4: Initial flashpage support
2020-11-10 15:07:35 +01:00
# The f2, f4 and f7 do not support the pagewise api
ifneq (,$(filter $(CPU_FAM),f2 f4 f7))
FEATURES_PROVIDED += periph_flashpage
endif
cpu/stm32: introduce CPU_FAM_SHORT variable This variable contains the short cpu family name: f1, f2, etc.
2020-05-26 11:12:06 +02:00
ifneq (,$(filter $(CPU_FAM),l0 l1))
cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
FEATURES_PROVIDED += periph_eeprom
endif
cpu/stm32: fix remaining occurence of stm32f1 cpu family
2020-05-30 18:59:36 +02:00
ifeq (f1,$(CPU_FAM))
cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
FEATURES_CONFLICT += periph_rtc:periph_rtt
FEATURES_CONFLICT_MSG += "On the STM32F1, the RTC and RTT map to the same hardware peripheral."
drivers/periph/rtt: add periph_rtt_set_counter feature Some periph_rtt implementations do not provide `rtt_set_counter()`. This adds `periph_rtt_set_counter` as feature to allow testing for its availability. The feature is provided at CPU level if periph_rtt is provided by the board for all CPUs implementing `rtt_set_counter()`.
2021-03-03 17:05:35 +01:00
FEATURES_PROVIDED += periph_rtt_set_counter
cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
endif
cpu/stm32: filter availability of RNG by CPU not by board. The old limitation is not valid anymore, we can evaluate $(CPU_MODEL) here directly. The output of make -C tests/periph_hwrng info-boards-supported | wc -w remains the same.
2020-05-29 17:37:05 +02:00
# Not all F4 and L0 parts implement a RNG.
cpu/stm32: stm32l011 lines doesn't provide hwrng
2020-10-13 15:30:07 +02:00
CPU_MODELS_WITHOUT_HWRNG = stm32f401% stm32f411% stm32f446% stm32l031% stm32l011%
cpu/stm32: add initial support for stm32u5 family
2021-12-15 15:53:53 +01:00
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l0 l4 l5 u5 wb))
cpu/stm32: filter availability of RNG by CPU not by board. The old limitation is not valid anymore, we can evaluate $(CPU_MODEL) here directly. The output of make -C tests/periph_hwrng info-boards-supported | wc -w remains the same.
2020-05-29 17:37:05 +02:00
ifeq (,$(filter $(CPU_MODELS_WITHOUT_HWRNG),$(CPU_MODEL)))
FEATURES_PROVIDED += periph_hwrng
endif
cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
endif
cpu/stm32: enable MPU for stm32mp1 stm32mp1 family has a MPU (Memory Processing Unit). Thus adds the feature. Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-08-03 00:25:58 +02:00
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l1 l4 mp1))
cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
FEATURES_PROVIDED += cortexm_mpu
endif
cpu/stm32: remove MPU feature from stm32l052t8
2020-08-21 15:19:49 +02:00
# only some stm32f3 have an MPU, stm32l052t8 provides an MPU but support is
# broken for cortex-m0+
STM32_WITH_MPU += stm32f303re stm32f303vc stm32f303ze
cpu/stm32: introduce unique directory for stm32 cpus
2020-05-03 14:35:01 +02:00
ifneq (,$(filter $(CPU_MODEL),$(STM32_WITH_MPU)))
FEATURES_PROVIDED += cortexm_mpu
endif
makefiles/kconfig: use two lists for boards and CPUs default configs This introduces KCONFIG_BOARD_CONFIG and KCONFIG_CPU_CONFIG variable for boards and CPUs (including common directories) to add default configuration files to be merged. The current approach, as it uses Makefile.features, would include boards first, not allowing them to override CPU configurations.
2021-12-10 16:04:46 +01:00
include $(RIOTCPU)/cortexm_common/Makefile.features
# Add stm32 configs after including cortexm_common so stm32 takes precedence
cpu/stm32: Add Kconfig dependency modeling
2021-05-19 17:41:00 +02:00
# This configuration enables modules that are only available when using Kconfig
# module modelling
ifeq (1, $(TEST_KCONFIG))
makefiles/kconfig: use two lists for boards and CPUs default configs This introduces KCONFIG_BOARD_CONFIG and KCONFIG_CPU_CONFIG variable for boards and CPUs (including common directories) to add default configuration files to be merged. The current approach, as it uses Makefile.features, would include boards first, not allowing them to override CPU configurations.
2021-12-10 16:04:46 +01:00
KCONFIG_CPU_CONFIG += $(RIOTCPU)/stm32/stm32.config
cpu/stm32: Add Kconfig dependency modeling
2021-05-19 17:41:00 +02:00
endif
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