ce1fe776cf
Some ESP32 boards (like my SparkFun ESP32 Thing) have a main clock crystal that runs at 26MHz, not 40MHz. RIOT appears to assume 40MHz. The mismatch causes the UART to not sync properly, resulting in garbage written to the terminal instead of log output. I’ve added: * A new board configuration constant ESP32_XTAL_FREQ that defaults to 40, but can be overridden by a board def or at build time to force a specific value (i.e. 26). * Some code spliced into system_clk_init() to check this constant and call rtc_clk_init() to set the correct frequency. * A copy of the rtf_clk_init() function from the ESP-IDF sources. Fixes #10272 |
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| esp-idf | ||
| xtensa | ||
| Makefile | ||
| README.md | ||
The subdirectories here contain third-party software components used by the RIOT port for ESP32.
esp
The files that are part of esp-open-rtos. The files in this directory are under the copyright of their respective owners. Please note the copyright notice in these files. All of these files are BSD Licensed as described in the file LICENSE.
esp-idf
The files in this directory and all subdirectories are from the Espressif IoT Development FrameworkESP-IDF, the official development framework for ESP32. All of these files are copyright of Espressif Systems (Shanghai) PTE LTD or their respective owners and licensed under the Apache License, Version 2.0. Please refer the copyright notice in these files for details.
xtensa
The files in this directory are from the FreeRTOS port for Xtensa configurable processors and Diamond processors. All of these files are copyright of Cadence Design Systems Inc. and licensed under the MIT license.