mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
317 lines
8.8 KiB
Plaintext
317 lines
8.8 KiB
Plaintext
/* Default entry point: */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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/* RTC fast memory holds RTC wake stub code,
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including from any source file named rtc_wake_stub*.c
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*/
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.rtc.text :
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{
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. = ALIGN(4);
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*(.rtc.literal .rtc.text)
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*rtc_wake_stub*.o(.literal .text .literal.* .text.*)
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} >rtc_iram_seg
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/* RTC bss, from any source file named rtc_wake_stub*.c */
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.rtc.bss (NOLOAD) :
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{
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/* part that is initialized if not waking up from deep sleep */
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_rtc_bss_start = ABSOLUTE(.);
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*rtc_wake_stub*.o(.bss .bss.*)
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*rtc_wake_stub*.o(COMMON)
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_rtc_bss_end = ABSOLUTE(.);
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/* part that saves some data for rtc periph module, this part is
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only initialized at power on reset */
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_rtc_bss_rtc_start = ABSOLUTE(.);
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*(.rtc.bss .rtc.bss.*)
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_rtc_bss_rtc_end = ABSOLUTE(.);
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} > rtc_slow_seg
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/* RTC slow memory holds RTC wake stub
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data/rodata, including from any source file
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named rtc_wake_stub*.c
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*/
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.rtc.data :
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{
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_rtc_data_start = ABSOLUTE(.);
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*(.rtc.data)
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*(.rtc.rodata)
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*rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
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_rtc_data_end = ABSOLUTE(.);
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} > rtc_slow_seg
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/* This section holds data that should not be initialized at power up
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and will be retained during deep sleep. The section located in
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RTC SLOW Memory area. User data marked with RTC_NOINIT_ATTR will be placed
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into this section. See the file "esp_attr.h" for more information.
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*/
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.rtc.noinit (NOLOAD):
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{
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. = ALIGN(4);
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_rtc_noinit_start = ABSOLUTE(.);
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*(.rtc_noinit .rtc_noinit.*)
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. = ALIGN(4) ;
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_rtc_noinit_end = ABSOLUTE(.);
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} > rtc_slow_seg
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/* Send .iram0 code to iram */
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.iram0.vectors :
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{
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/* Vectors go to IRAM */
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_init_start = ABSOLUTE(.);
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/* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
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. = 0x0;
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KEEP(*(.WindowVectors.text));
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. = 0x180;
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KEEP(*(.Level2InterruptVector.text));
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. = 0x1c0;
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KEEP(*(.Level3InterruptVector.text));
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. = 0x200;
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KEEP(*(.Level4InterruptVector.text));
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. = 0x240;
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KEEP(*(.Level5InterruptVector.text));
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. = 0x280;
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KEEP(**(.DebugExceptionVector.text));
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. = 0x2c0;
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KEEP(*(.NMIExceptionVector.text));
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. = 0x300;
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KEEP(*(.KernelExceptionVector.text));
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. = 0x340;
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KEEP(*(.UserExceptionVector.text));
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. = 0x3C0;
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KEEP(*(.DoubleExceptionVector.text));
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. = 0x400;
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*(.*Vector.literal)
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*(.UserEnter.literal);
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*(.UserEnter.text);
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. = ALIGN (16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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_init_end = ABSOLUTE(.);
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/* This goes here, not at top of linker script, so addr2line finds it last,
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and uses it in preference to the first symbol in IRAM */
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_iram_start = ABSOLUTE(0);
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} > iram0_0_seg
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/* If Bluetooth is not used, this DRAM section can be used as heap */
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. = _data_start_btdm; /* 0x3ffae6e0 */
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. = ALIGN (4);
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_sheap1 = ABSOLUTE(.);
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. = 0x3ffb0000;
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_eheap1 = ABSOLUTE(.);
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.iram0.text :
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{
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/* Code marked as running out of IRAM */
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_iram_text_start = ABSOLUTE(.);
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*(.iram1 .iram1.*)
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*libhal.a:(.literal .text .literal.* .text.*)
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*libgcc.a:(.literal .text .literal.* .text.*)
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*libgcov.a:(.literal .text .literal.* .text.*)
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*libc.a:*(.literal .text .literal.* .text.*)
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/* Xtensa basic functionality written in assembler should be placed in iram */
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*xtensa/*(.literal .text .literal.* .text.*)
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/* ESP-IDF parts that have to run in IRAM */
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*esp_idf_heap/*(.literal .text .literal.* .text.*)
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*esp_idf_spi_flash/*(.literal .text .literal.* .text.*)
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/* parts of RIOT that should to run in IRAM */
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*core/*(.literal .text .literal.* .text.*)
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*littlefs/*(.literal .text .literal.* .text.*)
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*littlefs2/*(.literal .text .literal.* .text.*)
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*newlib_syscalls_default/*(.literal .text .literal.* .text.*)
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*spiffs_fs/*(.literal .text .literal.* .text.*)
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*spiffs/*(.literal .text .literal.* .text.*)
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*syscalls.o(.literal .text .literal.* .text.*)
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*vfs/*(.literal .text .literal.* .text.*)
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/* part of the RIOT port that should run in IRAM */
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*cpu/*(.literal .text .literal.* .text.*)
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*esp_common/*(.literal .text .literal.* .text.*)
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*periph/*(.literal .text .literal.* .text.*)
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*mtd/**(.literal .text .literal.* .text.*)
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INCLUDE esp32.spiram.rom-functions-iram.ld
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_iram_text_end = ABSOLUTE(.);
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/* IRAM can't be used as heap since it only allows 32-bit aligned access */
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/*
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. = ALIGN (4);
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_sheap4 = ABSOLUTE(.);
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*/
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} > iram0_0_seg
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/* IRAM can't be used as heap since it only allows 32-bit aligned access */
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/*
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. = 0x400a0000;
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_eheap4 = ABSOLUTE(.);
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*/
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/* Starts at 0x3ffb000 if Bluetooth is not enabled, 0x3ffc0000 otherwise */
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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KEEP (*(SORT(.xfa.*)))
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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*(.dram1 .dram1.*)
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*libesp32.a:panic.o(.rodata .rodata.*)
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*libphy.a:(.rodata .rodata.*)
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*libsoc.a:rtc_clk.o(.rodata .rodata.*)
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*libapp_trace.a:(.rodata .rodata.*)
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*libgcov.a:(.rodata .rodata.*)
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*libheap.a:multi_heap.o(.rodata .rodata.*)
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*libheap.a:multi_heap_poisoning.o(.rodata .rodata.*)
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INCLUDE esp32.spiram.rom-functions-dram.ld
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_data_end = ABSOLUTE(.);
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. = ALIGN(4);
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} >dram0_0_seg
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/* This section holds data that should not be initialized at power up.
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The section located in Internal SRAM memory region. The macro _NOINIT
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can be used as attribute to place data into this section.
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See the esp_attr.h file for more information.
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*/
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.noinit (NOLOAD):
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{
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. = ALIGN(4);
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_noinit_start = ABSOLUTE(.);
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__noinit_start = ABSOLUTE(.);
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*(.noinit .noinit.*)
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. = ALIGN(4) ;
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_noinit_end = ABSOLUTE(.);
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__noinit_end = ABSOLUTE(.);
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} > dram0_0_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(.share.mem)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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_heap_start = ABSOLUTE(.);
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_sheap = ABSOLUTE(.);
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} >dram0_0_seg
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/* Reserved ROM/ETS data start at 0x3ffe000. */
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. = 0x3ffe0000;
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_heap_top = ABSOLUTE(.);
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_eheap = ABSOLUTE(.);
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/* Reserved ROM/ETS data region for PRO CPU: 0x3ffe0000 ... 0x3ffe440 */
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. = 0x3ffe0440;
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_sheap2 = ABSOLUTE(.);
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. = 0x3ffe4000;
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_eheap2 = ABSOLUTE(.);
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/* Reserved ROM/ETS data region for APP CPU: 0x3ffe4000 ... 0x3ffe4350 */
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. = 0x3ffe4350;
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_sheap3 = ABSOLUTE(.);
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. = 0x40000000;
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_eheap3 = ABSOLUTE(.);
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.flash.rodata :
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{
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_rodata_start = ABSOLUTE(.);
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*(.rodata)
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*(.rodata.*)
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KEEP (*(SORT(.roxfa.*)))
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table .gcc_except_table.*)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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. = (. + 3) & ~ 3;
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__eh_frame = ABSOLUTE(.);
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KEEP(*(.eh_frame))
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. = (. + 7) & ~ 3;
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/* C++ constructor and destructor tables, properly ordered: */
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__init_array_start = ABSOLUTE(.);
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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__init_array_end = ABSOLUTE(.);
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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_rodata_end = ABSOLUTE(.);
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/* Literals are also RO data. */
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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. = ALIGN(4);
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_thread_local_start = ABSOLUTE(.);
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*(.tdata)
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*(.tdata.*)
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*(.tbss)
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*(.tbss.*)
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_thread_local_end = ABSOLUTE(.);
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. = ALIGN(4);
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} >drom0_0_seg
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.flash.text :
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{
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_stext = .;
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_text_start = ABSOLUTE(.);
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/* place everything else in iram0_2_seg (cached ROM) */
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*(.literal .text .literal.* .text.* .stub)
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*(.gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_text_end = ABSOLUTE(.);
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_etext = .;
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/* Similar to _iram_start, this symbol goes here so it is
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resolved by addr2line in preference to the first symbol in
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the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} >iram0_2_seg
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}
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