mirror of
https://github.com/RIOT-OS/RIOT.git
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144 lines
3.4 KiB
C
144 lines
3.4 KiB
C
/*
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* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_lm4f120
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* @{
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*
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* @file uart.c
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* @brief Implementation of the low-level UART driver for the LM4F120
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*
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* @author Rakendra Thapa <rakendrathapa@gmail.com>
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*
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* @}
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*/
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#include <stdint.h>
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#include "assert.h"
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#include "cpu.h"
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#include "periph/uart.h"
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#include "periph_conf.h"
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/**
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* @brief UART device configurations
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*/
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static uart_isr_ctx_t config[UART_NUMOF];
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static int init_base(uart_t uart, uint32_t baudrate);
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/**
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* Configuring the UART console
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*/
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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/* Check the arguments */
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assert(uart == 0);
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/* Check to make sure the UART peripheral is present */
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if(!ROM_SysCtlPeripheralPresent(SYSCTL_PERIPH_UART0)){
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return UART_NODEV;
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}
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int res = init_base(uart, baudrate);
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if(res != UART_OK){
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return res;
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}
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/* save callbacks */
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config[uart].rx_cb = rx_cb;
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config[uart].arg = arg;
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/* ulBase = g_ulUARTBase[uart]; */
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switch (uart){
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#if UART_0_EN
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case UART_0:
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ROM_UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_EOT);
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ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
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ROM_UARTFIFOEnable(UART0_BASE);
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/* Enable the UART interrupt */
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NVIC_EnableIRQ(UART_0_IRQ_CHAN);
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/* Enable RX interrupt */
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UART0_IM_R = UART_IM_RXIM | UART_IM_RTIM;
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break;
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#endif
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#if UART_1_EN
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case UART_1:
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/* Enable the UART interrupt */
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NVIC_EnableIRQ(UART_1_IRQ_CHAN);
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break;
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#endif
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}
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return UART_OK;
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}
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static int init_base(uart_t uart, uint32_t baudrate)
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{
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switch(uart){
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#if UART_0_EN
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case UART_0:
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
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ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
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ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
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ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
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ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
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ROM_UARTDisable(UART0_BASE);
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ROM_UARTConfigSetExpClk(UART0_BASE,ROM_SysCtlClockGet(), baudrate,
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(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE |
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UART_CONFIG_WLEN_8));
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ROM_UARTEnable(UART0_BASE);
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break;
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#endif
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default:
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return UART_NODEV;
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}
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return UART_OK;
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}
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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for (size_t i = 0; i < len; i++) {
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ROM_UARTCharPut(UART0_BASE, (char)data[i]);
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}
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}
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void uart_poweron(uart_t uart)
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{
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ROM_UARTEnable(UART0_BASE);
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}
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void uart_poweroff(uart_t uart)
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{
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ROM_UARTDisable(UART0_BASE);
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}
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/**
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* The UART interrupt handler.
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*/
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void isr_uart0(void)
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{
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unsigned long ulStatus;
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ulStatus = ROM_UARTIntStatus(UART0_BASE, true);
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ROM_UARTIntClear(UART0_BASE, ulStatus);
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/* Are we interrupted due to a recieved character */
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if(ulStatus & (UART_INT_RX | UART_INT_RT))
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{
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while(ROM_UARTCharsAvail(UART0_BASE))
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{
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long lchar = ROM_UARTCharGetNonBlocking(UART0_BASE);
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config[UART_0].rx_cb(config[UART_0].arg, (uint8_t)lchar);
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}
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}
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cortexm_isr_end();
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}
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