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https://github.com/RIOT-OS/RIOT.git
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df37e69b90
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
244 lines
14 KiB
C
Executable File
244 lines
14 KiB
C
Executable File
/******************************************************************************
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* Filename: hw_udmachctl.h
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* Revised: $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
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* Revision: $Revision: 9735 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_UDMACHCTL_H__
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#define __HW_UDMACHCTL_H__
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//*****************************************************************************
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//
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// The following are defines for the UDMACHCTL register offsets.
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//
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//*****************************************************************************
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#define UDMACHCTL_O_SRCENDP 0x00000000
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#define UDMACHCTL_O_DSTENDP 0x00000004
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#define UDMACHCTL_O_CHCTL 0x00000008
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMACHCTL_O_SRCENDP register.
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//
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//*****************************************************************************
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#define UDMACHCTL_SRCENDP_ADDR_M \
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0xFFFFFFFF // Source address end pointer This
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// field points to the last address
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// of the uDMA transfer source
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// (inclusive). If the source
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// address is not incrementing (the
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// SRCINC field in the DMACHCTL
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// register is 0x3), then this
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// field points at the source
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// location itself (such as a
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// peripheral control register).
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#define UDMACHCTL_SRCENDP_ADDR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMACHCTL_O_DSTENDP register.
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//
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//*****************************************************************************
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#define UDMACHCTL_DSTENDP_ADDR_M \
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0xFFFFFFFF // Destination address end pointer
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// This field points to the last
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// address of the uDMA transfer
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// destination (inclusive). If the
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// destination address is not
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// incrementing (the DSTINC field
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// in the DMACHCTL register is
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// 0x3), then this field points at
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// the destination location itself
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// (such as a peripheral control
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// register).
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#define UDMACHCTL_DSTENDP_ADDR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// UDMACHCTL_O_CHCTL register.
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//
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//*****************************************************************************
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#define UDMACHCTL_CHCTL_DSTINC_M \
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0xC0000000 // Destination address increment
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// This field configures the
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// destination address increment.
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// The address increment value must
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// be equal or greater than the
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// value of the destination size
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// (DSTSIZE). 0x0: Byte - Increment
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// by 8-bit locations 0x1:
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// Half-word - Increment by 16-bit
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// locations 0x2: Word - Increment
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// by 32-bit locations 0x3: No
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// increment - Address remains set
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// to the value of the Destination
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// address end pointer (DMADSTENDP)
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// for the channel.
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#define UDMACHCTL_CHCTL_DSTINC_S 30
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#define UDMACHCTL_CHCTL_DSTSIZE_M \
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0x30000000 // Destination data size This
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// field configures the destination
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// item data size. Note: DSTSIZE
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// must be the same as SRCSIZE.
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// 0x0: Byte - 8-bit data size 0x1:
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// Half-word - 16-bit data size
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// 0x2: Word - 32-bit data size
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// 0x3: Reserved
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#define UDMACHCTL_CHCTL_DSTSIZE_S 28
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#define UDMACHCTL_CHCTL_SRCINC_M \
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0x0C000000 // Source address increment This
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// field configures the source
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// address increment. The address
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// increment value must be equal or
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// greater than the value of the
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// source size (SRCSIZE). 0x0: Byte
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// - Increment by 8-bit locations
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// 0x1: Half-word - Increment by
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// 16-bit locations 0x2: Word -
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// Increment by 32-bit locations
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// 0x3: No increment - Address
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// remains set to the value of the
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// Source address end pointer
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// (DMASRCENDP) for the channel.
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#define UDMACHCTL_CHCTL_SRCINC_S 26
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#define UDMACHCTL_CHCTL_SRCSIZE_M \
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0x03000000 // Source data size This field
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// configures the source item data
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// size. Note: SRCSIZE must be the
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// same as DSTSIZE. 0x0: Byte -
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// 8-bit data size 0x1: Half-word -
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// 16-bit data size 0x2: Word -
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// 32-bit data size 0x3: Reserved
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#define UDMACHCTL_CHCTL_SRCSIZE_S 24
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#define UDMACHCTL_CHCTL_ARBSIZE_M \
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0x0003C000 // Arbitration size This field
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// configures the number of
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// transfers that can occur before
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// the uDMA controller
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// re-arbitrates. The possible
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// arbitration rate configurations
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// represent powers of 2 and are
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// shown below. 0x0: 1 Transfer -
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// Arbitrates after each uDMA
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// transfer 0x1: 2 Transfers 0x2: 4
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// Transfers 0x3: 8 Transfers 0x4:
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// 16 Transfers 0x5: 32 Transfers
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// 0x6: 64 Transfers 0x7: 128
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// Transfers 0x8: 256 Transfers
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// 0x9: 512 Transfers 0xA-0xF: 1024
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// Transfers - In this
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// configuration, no arbitration
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// occurs during the uDMA transfer
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// because the maximum transfer
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// size is 1024.
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#define UDMACHCTL_CHCTL_ARBSIZE_S 14
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#define UDMACHCTL_CHCTL_XFERSIZE_M \
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0x00003FF0 // Transfer size (minus 1) This
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// field configures the total
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// number of items to transfer. The
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// value of this field is 1 less
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// than the number to transfer
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// (value 0 means transfer 1 item).
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// The maximum value for this
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// 10-bit field is 1023which
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// represents a transfer size of
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// 1024 items. The transfer size is
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// the number of items, not the
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// number of bytes, If the data
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// size is 32 bits, then this value
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// is the number of 32-bit words to
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// transfer. The uDMA controller
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// updates this field immediately
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// before entering the arbitration
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// process, so it contrains the
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// number of outstanding items that
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// is necessary to complete the
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// uDMA cycle.
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#define UDMACHCTL_CHCTL_XFERSIZE_S 4
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#define UDMACHCTL_CHCTL_NXTUSEBURST \
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0x00000008 // Next useburst This field
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// controls whether the Useburst
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// SET[n] bit is automatically set
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// for the last transfer of a
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// peripheral scatter-gather
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// operation. Normally, for the
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// last transfer, if the number of
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// remaining items to transfer is
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// less than the arbitration size,
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// the uDMA controller uses single
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// transfers to complete the
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// transaction. If this bit is set,
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// then the controller uses a burst
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// transfer to complete the last
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// transfer.
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#define UDMACHCTL_CHCTL_NXTUSEBURST_M \
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0x00000008
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#define UDMACHCTL_CHCTL_NXTUSEBURST_S 3
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#define UDMACHCTL_CHCTL_XFERMODE_M \
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0x00000007 // uDMA transfer mode This field
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// configures the operating mode of
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// the uDMA cycle. Refer to "Micro
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// Direct Memory Access - Transfer
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// Modes" for a detailed
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// explanation of transfer modes.
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// Because this register is in
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// system RAM, it has no reset
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// value. Therefore, this field
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// should be initialized to 0
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// before the channel is enabled.
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// 0x0: Stop 0x1: Basic 0x2:
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// Auto-request 0x3: Ping-pong 0x4:
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// Memory scatter-gather 0x5:
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// Alternate memory scatter-gather
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// 0x6: Peripheral scatter-gather
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// 0x7: Alternate peripheral
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// scatter-gather
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#define UDMACHCTL_CHCTL_XFERMODE_S 0
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#endif // __HW_UDMACHCTL_H__
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