mirror of
https://github.com/RIOT-OS/RIOT.git
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df37e69b90
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
1300 lines
71 KiB
C
Executable File
1300 lines
71 KiB
C
Executable File
/******************************************************************************
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* Filename: hw_gpio.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_GPIO_H__
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#define __HW_GPIO_H__
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//*****************************************************************************
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//
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// The following are defines for the GPIO register offsets.
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//
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//*****************************************************************************
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#define GPIO_O_DATA 0x00000000 // This is the data register. In
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// software control mode, values
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// written in the GPIODATA register
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// are transferred onto the GPOUT
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// pins if the respective pins have
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// been configured as outputs
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// through the GPIODIR register. A
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// read from GPIODATA returns the
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// last bit value written if the
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// respective pins are configured
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// as output, or it returns the
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// value on the corresponding input
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// GPIN bit when these are
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// configured as inputs.
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#define GPIO_O_DIR 0x00000400 // The DIR register is the data
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// direction register. All bits are
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// cleared by a reset; therefore,
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// the GPIO pins are input by
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// default.
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#define GPIO_O_IS 0x00000404 // The IS register is the
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// interrupt sense register.
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#define GPIO_O_IBE 0x00000408 // The IBE register is the
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// interrupt both-edges register.
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// When the corresponding bit in IS
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// is set to detect edges, bits set
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// to high in IBE configure the
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// corresponding pin to detect both
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// rising and falling edges,
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// regardless of the corresponding
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// bit in the IEV (interrupt event
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// register). Clearing a bit
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// configures the pin to be
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// controlled by IEV.
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#define GPIO_O_IEV 0x0000040C // The IEV register is the
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// interrupt event register. Bits
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// set to high in IEV configure the
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// corresponding pin to detect
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// rising edges or high levels,
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// depending on the corresponding
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// bit value in IS. Clearing a bit
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// configures the pin to detect
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// falling edges or low levels,
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// depending on the corresponding
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// bit value in IS.
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#define GPIO_O_IE 0x00000410 // The IE register is the
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// interrupt mask register. Bits
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// set to high in IE allow the
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// corresponding pins to trigger
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// their individual interrupts and
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// the combined GPIOINTR line.
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// Clearing a bit disables
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// interrupt triggering on that
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// pin.
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#define GPIO_O_RIS 0x00000414 // The RIS register is the raw
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// interrupt status register. Bits
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// read high in RIS reflect the
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// status of interrupts trigger
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// conditions detected (raw, before
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// masking), indicating that all
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// the requirements are met, before
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// they are finally allowed to
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// trigger by IE. Bits read as 0
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// indicate that corresponding
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// input pins have not initiated an
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// interrupt.
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#define GPIO_O_MIS 0x00000418 // The MIS register is the masked
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// interrupt status register. Bits
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// read high in MIS reflect the
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// status of input lines triggering
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// an interrupt. Bits read as low
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// indicate that either no
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// interrupt has been generated, or
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// the interrupt is masked. MIS is
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// the state of the interrupt after
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// masking.
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#define GPIO_O_IC 0x0000041C // The IC register is the
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// interrupt clear register.
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// Writing 1 to a bit in this
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// register clears the
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// corresponding interrupt edge
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// detection logic register.
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// Writing 0 has no effect.
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#define GPIO_O_AFSEL 0x00000420 // The AFSEL register is the mode
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// control select register. Writing
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// 1 to any bit in this register
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// selects the hardware
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// (peripheral) control for the
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// corresponding GPIO line. All
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// bits are cleared by a reset,
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// therefore no GPIO line is set to
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// hardware control by default.
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#define GPIO_O_GPIOLOCK 0x00000520 // A write of the value 0x4C4F434B
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// to the GPIOLOCK register unlocks
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// the GPIO commit register
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// (GPIOCR) for write access. A
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// write of any other value
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// reapplies the lock, preventing
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// any register updates. Any write
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// to the commit register (GPIOCR)
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// causes the lock register to be
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// locked.
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#define GPIO_O_GPIOCR 0x00000524 // The GPIOCR register is the
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// commit register. The value of
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// the GPIOCR register determines
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// which bits of the AFSEL register
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// is committed when a write to the
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// AFSEL register is performed. If
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// a bit in the GPIOCR register is
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// 0, the data being written to the
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// corresponding bit in the AFSEL
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// register is not committed and
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// retains its previous value. If a
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// bit in the GPIOCR register is
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// set to 1, the data being written
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// to the corresponding bit of the
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// AFSEL register is committed to
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// the register and will reflect
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// the new value. The contents of
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// the GPIOCR register can only be
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// modified if the GPIOLOCK
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// register is unlocked. Writes to
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// the GPIOCR register will be
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// ignored if the GPIOLOCK register
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// is locked. Any write to the
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// commit register causes the lock
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// register to be locked.
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#define GPIO_O_PMUX 0x00000700 // The PMUX register can be used
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// to output external decouple
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// control and clock_32k on I/O
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// pins. Decouple control can be
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// output on specific PB pins and
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// clock_32k can be output on a
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// specific PA or PB pin. These
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// features override the current
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// setting of the selected pin when
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// enabled. The pin is set to
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// output, pull-up and -down
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// disabled, and analog mode
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// disabled.
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#define GPIO_O_P_EDGE_CTRL 0x00000704 // The port edge control register
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// is used to control which edge of
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// each port input causes that port
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// to generate a power-up interrupt
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// to the system.
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#define GPIO_O_USB_CTRL 0x00000708 // This register is used to
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// control which edge of the USB
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// controller input generates a
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// power-up interrupt to the
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// system.
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#define GPIO_O_PI_IEN 0x00000710 // The power-up interrupt enable
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// register selects, for its
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// corresponding port A-D pin,
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// whether interrupts are enabled
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// or disabled.
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#define GPIO_O_IRQ_DETECT_ACK 0x00000718 // If the IRQ detect ACK register
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// is read, the value returned can
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// be used to determine which
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// enabled I/O port is responsible
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// for creating a power-up
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// interrupt to the system. Writing
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// the IRQ detect ACK register is
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// used to clear any number of
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// individual port bits that may be
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// signaling that an edge was
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// detected as configured by the
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// port edge control register and
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// the interrupt control register.
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// There is a self-clearing
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// function to this register that
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// generates a reset pulse to clear
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// any interrupt which has its
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// corresponding bit set to 1.
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#define GPIO_O_USB_IRQ_ACK 0x0000071C // Same functionality as
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// IRQ_DETECT_ACK, but for USB
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#define GPIO_O_IRQ_DETECT_UNMASK \
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0x00000720 // Same functionality as
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// IRQ_DETECT_ACK, but this
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// register handles masked
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// interrupts
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_DATA register.
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//
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//*****************************************************************************
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#define GPIO_DATA_DATA_M 0x000000FF // Input and output data
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#define GPIO_DATA_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_DIR register.
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//
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//*****************************************************************************
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#define GPIO_DIR_DIR_M 0x000000FF // Bits set: Corresponding pin is
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// output Bits cleared:
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// Corresponding pin is input
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#define GPIO_DIR_DIR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_IS register.
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//
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//*****************************************************************************
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#define GPIO_IS_IS_M 0x000000FF // Bits set: Level on
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// corresponding pin is detected
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// Bits cleared: Edge on
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// corresponding pin is detected
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#define GPIO_IS_IS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_IBE register.
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//
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//*****************************************************************************
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#define GPIO_IBE_IBE_M 0x000000FF // Bits set: Both edges on
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// corresponding pin trigger an
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// interrupt Bits cleared:
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// Interrupt generation event is
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// controlled by GPIOIEV Single
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// edge: Determined by
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// corresponding bit in GPIOIEV
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// register
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#define GPIO_IBE_IBE_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_IEV register.
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//
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//*****************************************************************************
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#define GPIO_IEV_IEV_M 0x000000FF // Bits set: Rising edges or high
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// levels on corresponding pin
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// trigger interrupts Bits cleared:
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// Falling edges or low levels on
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// corresponding pin trigger
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// interrupts
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#define GPIO_IEV_IEV_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_IE register.
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//
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//*****************************************************************************
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#define GPIO_IE_IE_M 0x000000FF // Bits set: Corresponding pin is
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// not masked Bits cleared:
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// Corresponding pin is masked
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#define GPIO_IE_IE_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_RIS register.
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//
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//*****************************************************************************
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#define GPIO_RIS_RIS_M 0x000000FF // Reflects the status of
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// interrupts trigger conditions
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// detected on pins (raw, before
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// masking) Bits set: Requirements
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// met by corresponding pins Bits
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// clear: Requirements not met
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#define GPIO_RIS_RIS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_MIS register.
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//
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//*****************************************************************************
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#define GPIO_MIS_MIS_M 0x000000FF // Masked value of interrupt due
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// to corresponding pin Bits clear:
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// GPIO line interrupt not active
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// Bits set: GPIO line asserting
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// interrupt
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#define GPIO_MIS_MIS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_IC register.
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//
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//*****************************************************************************
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#define GPIO_IC_IC_M 0x000000FF // Bit written as 1: Clears edge
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// detection logic Bit written as
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// 0: Has no effect
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#define GPIO_IC_IC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_AFSEL register.
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//
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//*****************************************************************************
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#define GPIO_AFSEL_AFSEL_M 0x000000FF // Bit set: Enables hardware
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// (peripheral) control mode Bit
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// cleared: Enables software
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// control mode
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#define GPIO_AFSEL_AFSEL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// GPIO_O_GPIOLOCK register.
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//
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//*****************************************************************************
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#define GPIO_GPIOLOCK_LOCK_M 0xFFFFFFFF // A read of this register returns
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// the following values: Locked:
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// 0x00000001 Unlocked: 0x00000000
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#define GPIO_GPIOLOCK_LOCK_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_GPIOCR register.
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//
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//*****************************************************************************
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#define GPIO_GPIOCR_CR_M 0x000000FF // On a bit-wise basis, any bit
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// set allows the corresponding
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// GPIOAFSEL bit to be set to its
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// alternate function.
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#define GPIO_GPIOCR_CR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_PMUX register.
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//
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//*****************************************************************************
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#define GPIO_PMUX_CKOEN 0x00000080 // Clock out enable When this bit
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// is set, the 32-kHz clock is
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// routed to either PA[0] or PB[7]
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// pins. PMUX.CKOPIN selects the
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// pin to use. This overrides the
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// current configuration setting
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// for this pin. The pullup or
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// pulldown is disabled and the
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// direction is set to output for
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// this pin.
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#define GPIO_PMUX_CKOEN_M 0x00000080
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#define GPIO_PMUX_CKOEN_S 7
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#define GPIO_PMUX_CKOPIN 0x00000010 // Decouple control pin select
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// This control only has relevance
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// when CKOEN is set. When 0, PA[0]
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// becomes the 32-kHz clock output.
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// When 1, PB[7] becomes the 32-kHz
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// clock output.
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#define GPIO_PMUX_CKOPIN_M 0x00000010
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#define GPIO_PMUX_CKOPIN_S 4
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#define GPIO_PMUX_DCEN 0x00000008 // Decouple control enable When
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// this bit is set, the on-die
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// digital regulator status is
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// routed to either PB[1] or PB[0]
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// pins. PMUX.DCPIN selects the pin
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// to use. This overrides the
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// current configuration setting
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// for this pin. The pullup or
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// pulldown is disabled and the
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// direction is set to output for
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// this pin.
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#define GPIO_PMUX_DCEN_M 0x00000008
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#define GPIO_PMUX_DCEN_S 3
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#define GPIO_PMUX_DCPIN 0x00000001 // Decouple control pin select
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// This control has relevance only
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// when DCEN is set. When 0, PB[1]
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// becomes the on-die digital
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// regulator status (1 indicates
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// the on-die digital regulator is
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// active); when 1, PB[0] becomes
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// the on-die digital regulator
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// status. NOTE: PB[1] and PB[0]
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// can also be controlled with
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// other override features. In
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// priority order for PB[1]: When
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// POR/BOD test mode is active,
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// PB[1] becomes the active low
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// brown-out detected indicator.
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// When DCEN is set and DCPIN is
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// not set, PB[1] becomes the
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// on-dir digital regulator status.
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// In priority order for PB[0]:
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// When POR/BOD test mode is
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// active, PB[0] becomes the
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// power-on-reset indicator. When
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// DCEN and DCPIN are set, PB[0]
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// becomes the on-die digital
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// regulator status.
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#define GPIO_PMUX_DCPIN_M 0x00000001
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#define GPIO_PMUX_DCPIN_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// GPIO_O_P_EDGE_CTRL register.
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//
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//*****************************************************************************
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#define GPIO_P_EDGE_CTRL_PDIRC7 0x80000000 // Port D bit 7 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
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#define GPIO_P_EDGE_CTRL_PDIRC7_M \
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0x80000000
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#define GPIO_P_EDGE_CTRL_PDIRC7_S 31
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#define GPIO_P_EDGE_CTRL_PDIRC6 0x40000000 // Port D bit 6 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
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#define GPIO_P_EDGE_CTRL_PDIRC6_M \
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0x40000000
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#define GPIO_P_EDGE_CTRL_PDIRC6_S 30
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#define GPIO_P_EDGE_CTRL_PDIRC5 0x20000000 // Port D bit 5 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
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#define GPIO_P_EDGE_CTRL_PDIRC5_M \
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0x20000000
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#define GPIO_P_EDGE_CTRL_PDIRC5_S 29
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#define GPIO_P_EDGE_CTRL_PDIRC4 0x10000000 // Port D bit 4 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
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#define GPIO_P_EDGE_CTRL_PDIRC4_M \
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0x10000000
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#define GPIO_P_EDGE_CTRL_PDIRC4_S 28
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#define GPIO_P_EDGE_CTRL_PDIRC3 0x08000000 // Port D bit 3 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
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#define GPIO_P_EDGE_CTRL_PDIRC3_M \
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0x08000000
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#define GPIO_P_EDGE_CTRL_PDIRC3_S 27
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#define GPIO_P_EDGE_CTRL_PDIRC2 0x04000000 // Port D bit 2 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
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#define GPIO_P_EDGE_CTRL_PDIRC2_M \
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0x04000000
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#define GPIO_P_EDGE_CTRL_PDIRC2_S 26
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#define GPIO_P_EDGE_CTRL_PDIRC1 0x02000000 // Port D bit 1 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
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#define GPIO_P_EDGE_CTRL_PDIRC1_M \
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0x02000000
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#define GPIO_P_EDGE_CTRL_PDIRC1_S 25
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#define GPIO_P_EDGE_CTRL_PDIRC0 0x01000000 // Port D bit 0 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
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#define GPIO_P_EDGE_CTRL_PDIRC0_M \
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0x01000000
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#define GPIO_P_EDGE_CTRL_PDIRC0_S 24
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#define GPIO_P_EDGE_CTRL_PCIRC7 0x00800000 // Port C bit 7 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
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#define GPIO_P_EDGE_CTRL_PCIRC7_M \
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0x00800000
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#define GPIO_P_EDGE_CTRL_PCIRC7_S 23
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#define GPIO_P_EDGE_CTRL_PCIRC6 0x00400000 // Port C bit 6 interrupt request
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// condition: 0: Rising 1: Falling
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// edge
|
|
#define GPIO_P_EDGE_CTRL_PCIRC6_M \
|
|
0x00400000
|
|
#define GPIO_P_EDGE_CTRL_PCIRC6_S 22
|
|
#define GPIO_P_EDGE_CTRL_PCIRC5 0x00200000 // Port C bit 5 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PCIRC5_M \
|
|
0x00200000
|
|
#define GPIO_P_EDGE_CTRL_PCIRC5_S 21
|
|
#define GPIO_P_EDGE_CTRL_PCIRC4 0x00100000 // Port C bit 4 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PCIRC4_M \
|
|
0x00100000
|
|
#define GPIO_P_EDGE_CTRL_PCIRC4_S 20
|
|
#define GPIO_P_EDGE_CTRL_PCIRC3 0x00080000 // Port C bit 3 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PCIRC3_M \
|
|
0x00080000
|
|
#define GPIO_P_EDGE_CTRL_PCIRC3_S 19
|
|
#define GPIO_P_EDGE_CTRL_PCIRC2 0x00040000 // Port C bit 2 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PCIRC2_M \
|
|
0x00040000
|
|
#define GPIO_P_EDGE_CTRL_PCIRC2_S 18
|
|
#define GPIO_P_EDGE_CTRL_PCIRC1 0x00020000 // Port C bit 1 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PCIRC1_M \
|
|
0x00020000
|
|
#define GPIO_P_EDGE_CTRL_PCIRC1_S 17
|
|
#define GPIO_P_EDGE_CTRL_PCIRC0 0x00010000 // Port C bit 0 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PCIRC0_M \
|
|
0x00010000
|
|
#define GPIO_P_EDGE_CTRL_PCIRC0_S 16
|
|
#define GPIO_P_EDGE_CTRL_PBIRC7 0x00008000 // Port B bit 7 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PBIRC7_M \
|
|
0x00008000
|
|
#define GPIO_P_EDGE_CTRL_PBIRC7_S 15
|
|
#define GPIO_P_EDGE_CTRL_PBIRC6 0x00004000 // Port B bit 6 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PBIRC6_M \
|
|
0x00004000
|
|
#define GPIO_P_EDGE_CTRL_PBIRC6_S 14
|
|
#define GPIO_P_EDGE_CTRL_PBIRC5 0x00002000 // Port B bit 5 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PBIRC5_M \
|
|
0x00002000
|
|
#define GPIO_P_EDGE_CTRL_PBIRC5_S 13
|
|
#define GPIO_P_EDGE_CTRL_PBIRC4 0x00001000 // Port B bit 4 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PBIRC4_M \
|
|
0x00001000
|
|
#define GPIO_P_EDGE_CTRL_PBIRC4_S 12
|
|
#define GPIO_P_EDGE_CTRL_PBIRC3 0x00000800 // Port B bit 3 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PBIRC3_M \
|
|
0x00000800
|
|
#define GPIO_P_EDGE_CTRL_PBIRC3_S 11
|
|
#define GPIO_P_EDGE_CTRL_PBIRC2 0x00000400 // Port B bit 2 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PBIRC2_M \
|
|
0x00000400
|
|
#define GPIO_P_EDGE_CTRL_PBIRC2_S 10
|
|
#define GPIO_P_EDGE_CTRL_PBIRC1 0x00000200 // Port B bit 1 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PBIRC1_M \
|
|
0x00000200
|
|
#define GPIO_P_EDGE_CTRL_PBIRC1_S 9
|
|
#define GPIO_P_EDGE_CTRL_PBIRC0 0x00000100 // Port B bit 0 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PBIRC0_M \
|
|
0x00000100
|
|
#define GPIO_P_EDGE_CTRL_PBIRC0_S 8
|
|
#define GPIO_P_EDGE_CTRL_PAIRC7 0x00000080 // Port A bit 7 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PAIRC7_M \
|
|
0x00000080
|
|
#define GPIO_P_EDGE_CTRL_PAIRC7_S 7
|
|
#define GPIO_P_EDGE_CTRL_PAIRC6 0x00000040 // Port A bit 6 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PAIRC6_M \
|
|
0x00000040
|
|
#define GPIO_P_EDGE_CTRL_PAIRC6_S 6
|
|
#define GPIO_P_EDGE_CTRL_PAIRC5 0x00000020 // Port A bit 5 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PAIRC5_M \
|
|
0x00000020
|
|
#define GPIO_P_EDGE_CTRL_PAIRC5_S 5
|
|
#define GPIO_P_EDGE_CTRL_PAIRC4 0x00000010 // Port A bit 4 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PAIRC4_M \
|
|
0x00000010
|
|
#define GPIO_P_EDGE_CTRL_PAIRC4_S 4
|
|
#define GPIO_P_EDGE_CTRL_PAIRC3 0x00000008 // Port A bit 3 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PAIRC3_M \
|
|
0x00000008
|
|
#define GPIO_P_EDGE_CTRL_PAIRC3_S 3
|
|
#define GPIO_P_EDGE_CTRL_PAIRC2 0x00000004 // Port A bit 2 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PAIRC2_M \
|
|
0x00000004
|
|
#define GPIO_P_EDGE_CTRL_PAIRC2_S 2
|
|
#define GPIO_P_EDGE_CTRL_PAIRC1 0x00000002 // Port A bit 1 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PAIRC1_M \
|
|
0x00000002
|
|
#define GPIO_P_EDGE_CTRL_PAIRC1_S 1
|
|
#define GPIO_P_EDGE_CTRL_PAIRC0 0x00000001 // Port A bit 0 interrupt request
|
|
// condition: 0: Rising 1: Falling
|
|
// edge
|
|
#define GPIO_P_EDGE_CTRL_PAIRC0_M \
|
|
0x00000001
|
|
#define GPIO_P_EDGE_CTRL_PAIRC0_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_USB_CTRL register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_USB_CTRL_USB_EDGE_CTL \
|
|
0x00000001 // Used to set the edge which
|
|
// triggers the USB power up
|
|
// interrupt 0: Rising 1: Falling
|
|
|
|
#define GPIO_USB_CTRL_USB_EDGE_CTL_M \
|
|
0x00000001
|
|
#define GPIO_USB_CTRL_USB_EDGE_CTL_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the GPIO_O_PI_IEN register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_PI_IEN_PDIEN7 0x80000000 // Port D bit 7 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PDIEN7_M 0x80000000
|
|
#define GPIO_PI_IEN_PDIEN7_S 31
|
|
#define GPIO_PI_IEN_PDIEN6 0x40000000 // Port D bit 6 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PDIEN6_M 0x40000000
|
|
#define GPIO_PI_IEN_PDIEN6_S 30
|
|
#define GPIO_PI_IEN_PDIEN5 0x20000000 // Port D bit 5 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PDIEN5_M 0x20000000
|
|
#define GPIO_PI_IEN_PDIEN5_S 29
|
|
#define GPIO_PI_IEN_PDIEN4 0x10000000 // Port D bit 4 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PDIEN4_M 0x10000000
|
|
#define GPIO_PI_IEN_PDIEN4_S 28
|
|
#define GPIO_PI_IEN_PDIEN3 0x08000000 // Port D bit 3 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PDIEN3_M 0x08000000
|
|
#define GPIO_PI_IEN_PDIEN3_S 27
|
|
#define GPIO_PI_IEN_PDIEN2 0x04000000 // Port D bit 2 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PDIEN2_M 0x04000000
|
|
#define GPIO_PI_IEN_PDIEN2_S 26
|
|
#define GPIO_PI_IEN_PDIEN1 0x02000000 // Port D bit 1 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PDIEN1_M 0x02000000
|
|
#define GPIO_PI_IEN_PDIEN1_S 25
|
|
#define GPIO_PI_IEN_PDIEN0 0x01000000 // Port D bit 0 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PDIEN0_M 0x01000000
|
|
#define GPIO_PI_IEN_PDIEN0_S 24
|
|
#define GPIO_PI_IEN_PCIEN7 0x00800000 // Port C bit 7 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PCIEN7_M 0x00800000
|
|
#define GPIO_PI_IEN_PCIEN7_S 23
|
|
#define GPIO_PI_IEN_PCIEN6 0x00400000 // Port C bit 6 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PCIEN6_M 0x00400000
|
|
#define GPIO_PI_IEN_PCIEN6_S 22
|
|
#define GPIO_PI_IEN_PCIEN5 0x00200000 // Port C bit 5 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PCIEN5_M 0x00200000
|
|
#define GPIO_PI_IEN_PCIEN5_S 21
|
|
#define GPIO_PI_IEN_PCIEN4 0x00100000 // Port C bit 4 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PCIEN4_M 0x00100000
|
|
#define GPIO_PI_IEN_PCIEN4_S 20
|
|
#define GPIO_PI_IEN_PCIEN3 0x00080000 // Port C bit 3 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PCIEN3_M 0x00080000
|
|
#define GPIO_PI_IEN_PCIEN3_S 19
|
|
#define GPIO_PI_IEN_PCIEN2 0x00040000 // Port C bit 2 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PCIEN2_M 0x00040000
|
|
#define GPIO_PI_IEN_PCIEN2_S 18
|
|
#define GPIO_PI_IEN_PCIEN1 0x00020000 // Port C bit 1 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PCIEN1_M 0x00020000
|
|
#define GPIO_PI_IEN_PCIEN1_S 17
|
|
#define GPIO_PI_IEN_PCIEN0 0x00010000 // Port C bit 0 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PCIEN0_M 0x00010000
|
|
#define GPIO_PI_IEN_PCIEN0_S 16
|
|
#define GPIO_PI_IEN_PBIEN7 0x00008000 // Port B bit 7 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PBIEN7_M 0x00008000
|
|
#define GPIO_PI_IEN_PBIEN7_S 15
|
|
#define GPIO_PI_IEN_PBIEN6 0x00004000 // Port B bit 6 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PBIEN6_M 0x00004000
|
|
#define GPIO_PI_IEN_PBIEN6_S 14
|
|
#define GPIO_PI_IEN_PBIEN5 0x00002000 // Port B bit 5 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PBIEN5_M 0x00002000
|
|
#define GPIO_PI_IEN_PBIEN5_S 13
|
|
#define GPIO_PI_IEN_PBIEN4 0x00001000 // Port B bit 4 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PBIEN4_M 0x00001000
|
|
#define GPIO_PI_IEN_PBIEN4_S 12
|
|
#define GPIO_PI_IEN_PBIEN3 0x00000800 // Port B bit 3 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PBIEN3_M 0x00000800
|
|
#define GPIO_PI_IEN_PBIEN3_S 11
|
|
#define GPIO_PI_IEN_PBIEN2 0x00000400 // Port B bit 2 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PBIEN2_M 0x00000400
|
|
#define GPIO_PI_IEN_PBIEN2_S 10
|
|
#define GPIO_PI_IEN_PBIEN1 0x00000200 // Port B bit 1 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PBIEN1_M 0x00000200
|
|
#define GPIO_PI_IEN_PBIEN1_S 9
|
|
#define GPIO_PI_IEN_PBIEN0 0x00000100 // Port B bit 0 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PBIEN0_M 0x00000100
|
|
#define GPIO_PI_IEN_PBIEN0_S 8
|
|
#define GPIO_PI_IEN_PAIEN7 0x00000080 // Port A bit 7 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PAIEN7_M 0x00000080
|
|
#define GPIO_PI_IEN_PAIEN7_S 7
|
|
#define GPIO_PI_IEN_PAIEN6 0x00000040 // Port A bit 6 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PAIEN6_M 0x00000040
|
|
#define GPIO_PI_IEN_PAIEN6_S 6
|
|
#define GPIO_PI_IEN_PAIEN5 0x00000020 // Port A bit 5 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PAIEN5_M 0x00000020
|
|
#define GPIO_PI_IEN_PAIEN5_S 5
|
|
#define GPIO_PI_IEN_PAIEN4 0x00000010 // Port A bit 4 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PAIEN4_M 0x00000010
|
|
#define GPIO_PI_IEN_PAIEN4_S 4
|
|
#define GPIO_PI_IEN_PAIEN3 0x00000008 // Port A bit 3 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PAIEN3_M 0x00000008
|
|
#define GPIO_PI_IEN_PAIEN3_S 3
|
|
#define GPIO_PI_IEN_PAIEN2 0x00000004 // Port A bit 2 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PAIEN2_M 0x00000004
|
|
#define GPIO_PI_IEN_PAIEN2_S 2
|
|
#define GPIO_PI_IEN_PAIEN1 0x00000002 // Port A bit 1 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PAIEN1_M 0x00000002
|
|
#define GPIO_PI_IEN_PAIEN1_S 1
|
|
#define GPIO_PI_IEN_PAIEN0 0x00000001 // Port A bit 0 interrupt enable:
|
|
// 1: Enabled 2: Disabled
|
|
#define GPIO_PI_IEN_PAIEN0_M 0x00000001
|
|
#define GPIO_PI_IEN_PAIEN0_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_IRQ_DETECT_ACK register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK7 \
|
|
0x80000000 // Port D bit 7 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK7_M \
|
|
0x80000000
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK7_S 31
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK6 \
|
|
0x40000000 // Port D bit 6 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK6_M \
|
|
0x40000000
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK6_S 30
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK5 \
|
|
0x20000000 // Port D bit 5 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK5_M \
|
|
0x20000000
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK5_S 29
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK4 \
|
|
0x10000000 // Port D bit 4 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK4_M \
|
|
0x10000000
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK4_S 28
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK3 \
|
|
0x08000000 // Port D bit 3 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK3_M \
|
|
0x08000000
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK3_S 27
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK2 \
|
|
0x04000000 // Port D bit 2 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK2_M \
|
|
0x04000000
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK2_S 26
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK1 \
|
|
0x02000000 // Port D bit 1 masked interrupt
|
|
// status: 1: Detected0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK1_M \
|
|
0x02000000
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK1_S 25
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK0 \
|
|
0x01000000 // Port D bit 0 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK0_M \
|
|
0x01000000
|
|
#define GPIO_IRQ_DETECT_ACK_PDIACK0_S 24
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK7 \
|
|
0x00800000 // Port C bit 7 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK7_M \
|
|
0x00800000
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK7_S 23
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK6 \
|
|
0x00400000 // Port C bit 6 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK6_M \
|
|
0x00400000
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK6_S 22
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK5 \
|
|
0x00200000 // Port C bit 5 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK5_M \
|
|
0x00200000
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK5_S 21
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK4 \
|
|
0x00100000 // Port C bit 4 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK4_M \
|
|
0x00100000
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK4_S 20
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK3 \
|
|
0x00080000 // Port C bit 3 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK3_M \
|
|
0x00080000
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK3_S 19
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK2 \
|
|
0x00040000 // Port C bit 2 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK2_M \
|
|
0x00040000
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK2_S 18
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK1 \
|
|
0x00020000 // Port C bit 1 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK1_M \
|
|
0x00020000
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK1_S 17
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK0 \
|
|
0x00010000 // Port C bit 0 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK0_M \
|
|
0x00010000
|
|
#define GPIO_IRQ_DETECT_ACK_PCIACK0_S 16
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK7 \
|
|
0x00008000 // Port B bit 7 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK7_M \
|
|
0x00008000
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK7_S 15
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK6 \
|
|
0x00004000 // Port B bit 6 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK6_M \
|
|
0x00004000
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK6_S 14
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK5 \
|
|
0x00002000 // Port B bit 5 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK5_M \
|
|
0x00002000
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK5_S 13
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK4 \
|
|
0x00001000 // Port B bit 4 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK4_M \
|
|
0x00001000
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK4_S 12
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK3 \
|
|
0x00000800 // Port B bit 3 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK3_M \
|
|
0x00000800
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK3_S 11
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK2 \
|
|
0x00000400 // Port B bit 2 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK2_M \
|
|
0x00000400
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK2_S 10
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK1 \
|
|
0x00000200 // Port B bit 1 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK1_M \
|
|
0x00000200
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK1_S 9
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK0 \
|
|
0x00000100 // Port B bit 0 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK0_M \
|
|
0x00000100
|
|
#define GPIO_IRQ_DETECT_ACK_PBIACK0_S 8
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK7 \
|
|
0x00000080 // Port A bit 7 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK7_M \
|
|
0x00000080
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK7_S 7
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK6 \
|
|
0x00000040 // Port A bit 6 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK6_M \
|
|
0x00000040
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK6_S 6
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK5 \
|
|
0x00000020 // Port A bit 5 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK5_M \
|
|
0x00000020
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK5_S 5
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK4 \
|
|
0x00000010 // Port A bit 4 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK4_M \
|
|
0x00000010
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK4_S 4
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK3 \
|
|
0x00000008 // Port A bit 3 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK3_M \
|
|
0x00000008
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK3_S 3
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK2 \
|
|
0x00000004 // Port A bit 2 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK2_M \
|
|
0x00000004
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK2_S 2
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK1 \
|
|
0x00000002 // Port A bit 1 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK1_M \
|
|
0x00000002
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK1_S 1
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK0 \
|
|
0x00000001 // Port A bit 0 masked interrupt
|
|
// status: 1: Detected 0: Not
|
|
// detected
|
|
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK0_M \
|
|
0x00000001
|
|
#define GPIO_IRQ_DETECT_ACK_PAIACK0_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_USB_IRQ_ACK register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_USB_IRQ_ACK_USBACK 0x00000001 // USB masked interrupt status: 1:
|
|
// Detected 0: Not detected
|
|
#define GPIO_USB_IRQ_ACK_USBACK_M \
|
|
0x00000001
|
|
#define GPIO_USB_IRQ_ACK_USBACK_S 0
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the
|
|
// GPIO_O_IRQ_DETECT_UNMASK register.
|
|
//
|
|
//*****************************************************************************
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK7 \
|
|
0x80000000 // Port D bit 7 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK7_M \
|
|
0x80000000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK7_S 31
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK6 \
|
|
0x40000000 // Port D bit 6 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK6_M \
|
|
0x40000000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK6_S 30
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK5 \
|
|
0x20000000 // Port D bit 5 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK5_M \
|
|
0x20000000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK5_S 29
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK4 \
|
|
0x10000000 // Port D bit 4 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK4_M \
|
|
0x10000000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK4_S 28
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK3 \
|
|
0x08000000 // Port D bit 3 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK3_M \
|
|
0x08000000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK3_S 27
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK2 \
|
|
0x04000000 // Port D bit 2 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK2_M \
|
|
0x04000000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK2_S 26
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK1 \
|
|
0x02000000 // Port D bit 1 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK1_M \
|
|
0x02000000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK1_S 25
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK0 \
|
|
0x01000000 // Port D bit 0 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK0_M \
|
|
0x01000000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PDIACK0_S 24
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK7 \
|
|
0x00800000 // Port C bit 7 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK7_M \
|
|
0x00800000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK7_S 23
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK6 \
|
|
0x00400000 // Port C bit 6 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK6_M \
|
|
0x00400000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK6_S 22
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK5 \
|
|
0x00200000 // Port C bit 5 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK5_M \
|
|
0x00200000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK5_S 21
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK4 \
|
|
0x00100000 // Port C bit 4 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK4_M \
|
|
0x00100000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK4_S 20
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK3 \
|
|
0x00080000 // Port C bit 3 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK3_M \
|
|
0x00080000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK3_S 19
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK2 \
|
|
0x00040000 // Port C bit 2 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK2_M \
|
|
0x00040000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK2_S 18
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK1 \
|
|
0x00020000 // Port C bit 1 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK1_M \
|
|
0x00020000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK1_S 17
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK0 \
|
|
0x00010000 // Port C bit 0 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK0_M \
|
|
0x00010000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PCIACK0_S 16
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK7 \
|
|
0x00008000 // Port B bit 7 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK7_M \
|
|
0x00008000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK7_S 15
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK6 \
|
|
0x00004000 // Port B bit 6 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK6_M \
|
|
0x00004000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK6_S 14
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK5 \
|
|
0x00002000 // Port B bit 5 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK5_M \
|
|
0x00002000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK5_S 13
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK4 \
|
|
0x00001000 // Port B bit 4 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK4_M \
|
|
0x00001000
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK4_S 12
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK3 \
|
|
0x00000800 // Port B bit 3 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK3_M \
|
|
0x00000800
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK3_S 11
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK2 \
|
|
0x00000400 // Port B bit 2 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK2_M \
|
|
0x00000400
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK2_S 10
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK1 \
|
|
0x00000200 // Port B bit 1 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK1_M \
|
|
0x00000200
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK1_S 9
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK0 \
|
|
0x00000100 // Port B bit 0 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK0_M \
|
|
0x00000100
|
|
#define GPIO_IRQ_DETECT_UNMASK_PBIACK0_S 8
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK7 \
|
|
0x00000080 // Port A bit 7 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK7_M \
|
|
0x00000080
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK7_S 7
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK6 \
|
|
0x00000040 // Port A bit 6 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK6_M \
|
|
0x00000040
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK6_S 6
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK5 \
|
|
0x00000020 // Port A bit 5 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK5_M \
|
|
0x00000020
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK5_S 5
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK4 \
|
|
0x00000010 // Port A bit 4 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK4_M \
|
|
0x00000010
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK4_S 4
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK3 \
|
|
0x00000008 // Port A bit 3 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK3_M \
|
|
0x00000008
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK3_S 3
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK2 \
|
|
0x00000004 // Port A bit 2 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK2_M \
|
|
0x00000004
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK2_S 2
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK1 \
|
|
0x00000002 // Port A bit 1 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK1_M \
|
|
0x00000002
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK1_S 1
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK0 \
|
|
0x00000001 // Port A bit 0 unmasked interrupt
|
|
// status: 1: Detected 0:
|
|
// Undetected
|
|
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK0_M \
|
|
0x00000001
|
|
#define GPIO_IRQ_DETECT_UNMASK_PAIACK0_S 0
|
|
|
|
|
|
#endif // __HW_GPIO_H__
|
|
|