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85 lines
2.1 KiB
C
85 lines
2.1 KiB
C
/*
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* Copyright (C) 2018 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2018-2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Default STM32F7 clock configuration for 216MHz boards
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
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#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock PLL settings (216MHz)
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* @{
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*/
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/* The following parameters configure a 216MHz system clock with HSE (8MHz,
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16MHz or 25MHz) or HSI (16MHz) as PLL input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
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#define CONFIG_CLOCK_PLL_M (25)
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#else
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#define CONFIG_CLOCK_PLL_M (4)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(25))
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#define CONFIG_CLOCK_PLL_N (432)
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#elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE == MHZ(8))
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#define CONFIG_CLOCK_PLL_N (216)
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#else
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#define CONFIG_CLOCK_PLL_N (108)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_P
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#define CONFIG_CLOCK_PLL_P (2)
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (9)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (8)
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#endif
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/** @} */
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/**
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* @name Clock bus settings (APB1 and APB2)
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* @{
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*/
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (4) /* max 54MHz */
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#endif
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (2) /* max 108MHz */
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#endif
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/** @} */
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#if CLOCK_CORECLOCK > MHZ(216)
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#error "SYSCLK cannot exceed 216MHz"
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H */
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/** @} */
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