mirror of
https://github.com/RIOT-OS/RIOT.git
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273 lines
7.1 KiB
C
273 lines
7.1 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_stm32f4discovery
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the STM32F4discovery board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Peter Kietzmann <peter.kietzmann@haw-hamburg.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 168MHz */
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#define CLOCK_CORECLOCK (168000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (168)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (7)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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},
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_1_ISR isr_tim5
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_D, 9),
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.tx_pin = GPIO_PIN(PORT_D, 8),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 3,
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.dma_chan = 4
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#endif
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}
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_0_DMA_ISR (isr_dma1_stream6)
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#define UART_1_ISR (isr_usart3)
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#define UART_1_DMA_ISR (isr_dma1_stream3)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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*
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* We need to define the following fields:
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* PIN, device (ADCx), channel
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* @{
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*/
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#define ADC_CONFIG { \
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{GPIO_PIN(PORT_A, 1), 0, 1}, \
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{GPIO_PIN(PORT_A, 4), 0, 4}, \
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{GPIO_PIN(PORT_C, 1), 1, 11}, \
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{GPIO_PIN(PORT_C, 2), 1, 12} \
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}
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#define ADC_NUMOF (4)
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/** @} */
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/**
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* @name DAC configuration
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* @{
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*/
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static const dac_conf_t dac_config[] = {
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{ .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
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{ .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
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};
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#define DAC_NUMOF (sizeof(dac_config) / sizeof(dac_config[0]))
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM1,
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.rcc_mask = RCC_APB2ENR_TIM1EN,
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.chan = { { .pin = GPIO_PIN(PORT_E, 9), .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 2 },
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{ .pin = GPIO_PIN(PORT_E, 14), .cc_chan = 3 } },
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.af = GPIO_AF1,
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.bus = APB2
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},
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{
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.dev = TIM3,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_B, 5), .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_B, 0), .cc_chan = 2 },
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{ .pin = GPIO_PIN(PORT_B, 1), .cc_chan = 3 } },
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.af = GPIO_AF2,
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.bus = APB1
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 42000000Hz */
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7, /* -> 164062Hz */
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6, /* -> 328125Hz */
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4, /* -> 1312500Hz */
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2, /* -> 5250000Hz */
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1 /* -> 10500000Hz */
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},
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{ /* for APB2 @ 84000000Hz */
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7, /* -> 328125Hz */
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7, /* -> 328125Hz */
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5, /* -> 1312500Hz */
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3, /* -> 5250000Hz */
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2 /* -> 10500000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_PIN(PORT_A, 4),
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.af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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},
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{
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.dev = SPI2,
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.mosi_pin = GPIO_PIN(PORT_B, 15),
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.miso_pin = GPIO_PIN(PORT_B, 14),
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.sclk_pin = GPIO_PIN(PORT_B, 13),
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.cs_pin = GPIO_PIN(PORT_B, 12),
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.af = GPIO_AF5,
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.rccmask = RCC_APB1ENR_SPI2EN,
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.apbbus = APB1
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (CLOCK_APB1)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
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#define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PORT GPIOB
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#define I2C_0_SCL_PIN 6
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#define I2C_0_SCL_AF 4
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#define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
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#define I2C_0_SDA_PORT GPIOB
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#define I2C_0_SDA_PIN 7
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#define I2C_0_SDA_AF 4
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#define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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