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https://github.com/RIOT-OS/RIOT.git
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254 lines
6.8 KiB
C
254 lines
6.8 KiB
C
/*
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* Copyright (C) 2015-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32f4
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include "periph_cpu_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Available number of ADC devices
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*/
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#if defined(CPU_MODEL_STM32F401RE)
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#define ADC_DEVS (1U)
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#elif defined(CPU_MODEL_STM32F407VG) || defined(CPU_MODEL_STM32F415RG)
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#define ADC_DEVS (3U)
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#endif
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/**
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* @brief Overwrite the default gpio_t type definition
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* @{
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*/
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#define HAVE_GPIO_T
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typedef uint32_t gpio_t;
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/** @} */
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/**
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* @brief Definition of a fitting UNDEF value
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*/
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#define GPIO_UNDEF (0xffffffff)
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/**
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* @brief Define a CPU specific GPIO pin generator macro
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*/
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#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
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/**
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* @brief declare needed generic SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/** @} */
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/**
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* @brief Override the ADC resolution configuration
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* @{
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*/
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_6BIT = 0x03000000, /**< ADC resolution: 6 bit */
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ADC_RES_8BIT = 0x02000000, /**< ADC resolution: 8 bit */
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ADC_RES_10BIT = 0x01000000, /**< ADC resolution: 10 bit */
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ADC_RES_12BIT = 0x00000000, /**< ADC resolution: 12 bit */
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ADC_RES_14BIT = 1, /**< ADC resolution: 14 bit (not supported) */
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ADC_RES_16BIT = 2 /**< ADC resolution: 16 bit (not supported)*/
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} adc_res_t;
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/** @} */
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/**
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* @brief Available ports on the STM32F4 family
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*/
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enum {
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PORT_A = 0, /**< port A */
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PORT_B = 1, /**< port B */
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PORT_C = 2, /**< port C */
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PORT_D = 3, /**< port D */
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PORT_E = 4, /**< port E */
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PORT_F = 5, /**< port F */
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PORT_G = 6, /**< port G */
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PORT_H = 7, /**< port H */
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PORT_I = 8 /**< port I */
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};
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/**
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* @brief Available MUX values for configuring a pin's alternate function
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*/
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typedef enum {
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GPIO_AF0 = 0, /**< use alternate function 0 */
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GPIO_AF1, /**< use alternate function 1 */
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GPIO_AF2, /**< use alternate function 2 */
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GPIO_AF3, /**< use alternate function 3 */
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GPIO_AF4, /**< use alternate function 4 */
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GPIO_AF5, /**< use alternate function 5 */
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GPIO_AF6, /**< use alternate function 6 */
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GPIO_AF7, /**< use alternate function 7 */
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GPIO_AF8, /**< use alternate function 8 */
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GPIO_AF9, /**< use alternate function 9 */
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GPIO_AF10, /**< use alternate function 10 */
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GPIO_AF11, /**< use alternate function 11 */
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GPIO_AF12, /**< use alternate function 12 */
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GPIO_AF13, /**< use alternate function 13 */
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GPIO_AF14 /**< use alternate function 14 */
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} gpio_af_t;
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/**
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* @brief Structure for UART configuration data
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* @{
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*/
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typedef struct {
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USART_TypeDef *dev; /**< UART device base register address */
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uint32_t rcc_mask; /**< bit in clock enable register */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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gpio_af_t af; /**< alternate pin function to use */
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uint8_t irqn; /**< IRQ channel */
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uint8_t dma_stream; /**< DMA stream used for TX */
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uint8_t dma_chan; /**< DMA channel used for TX */
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} uart_conf_t;
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/** @} */
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/**
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* @brief ADC channel configuration data
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*/
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typedef struct {
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gpio_t pin; /**< pin connected to the channel */
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uint8_t dev; /**< ADCx - 1 device used for the channel */
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uint8_t chan; /**< CPU ADC channel connected to the pin */
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uint8_t rcc; /**< bit in the RCC APB2 enable register */
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} adc_conf_t;
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/**
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* @brief Configure the alternate function for the given pin
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*
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* @note This is meant for internal use in STM32F4 peripheral drivers only
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*
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* @param[in] pin pin to configure
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* @param[in] af alternate function to use
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*/
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void gpio_init_af(gpio_t pin, gpio_af_t af);
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/**
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* @brief Configure the given pin to be used as ADC input
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*
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* @param[in] pin pin to configure
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*/
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void gpio_init_analog(gpio_t pin);
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/**
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* @brief Power on the DMA device the given stream belongs to
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*
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* @param[in] stream logical DMA stream
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*/
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static inline void dma_poweron(int stream)
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{
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if (stream < 8) {
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
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} else {
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RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
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}
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}
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/**
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* @brief Get DMA base register
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*
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* For simplifying DMA stream handling, we map the DMA channels transparently to
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* one integer number, such that DMA1 stream0 equals 0, DMA2 stream0 equals 8,
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* DMA2 stream 7 equals 15 and so on.
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*
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* @param[in] stream logical DMA stream
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*/
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static inline DMA_TypeDef *dma_base(int stream)
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{
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return (stream < 8) ? DMA1 : DMA2;
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}
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/**
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* @brief Get the DMA stream base address
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*
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* @param[in] stream logical DMA stream
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*
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* @return base address for the selected DMA stream
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*/
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static inline DMA_Stream_TypeDef *dma_stream(int stream)
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{
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uint32_t base = (uint32_t)dma_base(stream);
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return (DMA_Stream_TypeDef *)(base + (0x10 + (0x18 * (stream & 0x7))));
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}
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/**
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* @brief Select high or low DMA interrupt register based on stream number
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*
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* @param[in] stream logical DMA stream
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*
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* @return 0 for streams 0-3, 1 for streams 3-7
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*/
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static inline int dma_hl(int stream)
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{
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return ((stream & 0x4) >> 2);
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}
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/**
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* @brief Get the interrupt flag clear bit position in the DMA LIFCR register
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*
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* @param[in] stream logical DMA stream
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*/
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static inline uint32_t dma_ifc(int stream)
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{
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switch (stream & 0x3) {
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case 0:
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return (1 << 5);
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case 1:
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return (1 << 11);
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case 2:
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return (1 << 21);
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case 3:
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return (1 << 27);
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default:
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return 0;
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}
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}
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static inline void dma_isr_enable(int stream)
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{
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if (stream < 7) {
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NVIC_EnableIRQ((IRQn_Type)((int)DMA1_Stream0_IRQn + stream));
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}
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else if (stream == 7) {
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NVIC_EnableIRQ(DMA1_Stream7_IRQn);
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}
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else if (stream < 13) {
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NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream0_IRQn + (stream - 8)));
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}
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else if (stream < 16) {
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NVIC_EnableIRQ((IRQn_Type)((int)DMA2_Stream5_IRQn + (stream - 13)));
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}
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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