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https://github.com/RIOT-OS/RIOT.git
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349 lines
12 KiB
C
349 lines
12 KiB
C
/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 OTA keys S.A.
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* 2017 HAW-Hamburg
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* 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration for L5 family
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Michel Rottleuthner <michel.rottleuthner@haw-hamburg.de>
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* @author Francisco Molina <francois-xavier.molina@inria.fr>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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/* map CMSIS defines not present in wb and l5 families */
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#define RCC_PLLCFGR_PLLSRC_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0)
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#define RCC_PLLCFGR_PLLSRC_HSI (RCC_PLLCFGR_PLLSRC_1)
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#define RCC_PLLCFGR_PLLSRC_MSI (RCC_PLLCFGR_PLLSRC_0)
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#define RCC_CFGR_SW_MSI (0x00000000U)
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#define RCC_CFGR_SW_HSI (RCC_CFGR_SW_0)
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#define RCC_CFGR_SW_HSE (RCC_CFGR_SW_1)
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#define RCC_CFGR_SW_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0)
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#define RCC_CFGR_SWS_MSI (0x00000000U)
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#define RCC_CFGR_SWS_HSI (RCC_CFGR_SWS_0)
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#define RCC_CFGR_SWS_HSE (RCC_CFGR_SWS_1)
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#define RCC_CFGR_SWS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0)
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/* PLL configuration */
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/* figure out which input to use */
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#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI
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#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI)
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#else
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#define PLL_SRC 0
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#endif
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/* check configuration and get the corresponding bitfields */
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#if (CONFIG_CLOCK_PLL_M < 1 || CONFIG_CLOCK_PLL_M > 16)
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#error "PLL configuration: PLL M value is out of range"
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#endif
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#define PLL_M ((CONFIG_CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#if (CONFIG_CLOCK_PLL_N < 8 || CONFIG_CLOCK_PLL_N > 86)
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#error "PLL configuration: PLL N value is out of range"
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#endif
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#define PLL_N (CONFIG_CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#if (CONFIG_CLOCK_PLL_R == 2)
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#define PLL_R (0)
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#elif (CONFIG_CLOCK_PLL_R == 4)
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#define PLL_R (RCC_PLLCFGR_PLLR_0)
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#elif (CONFIG_CLOCK_PLL_R == 6)
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#define PLL_R (RCC_PLLCFGR_PLLR_1)
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#elif (CONFIG_CLOCK_PLL_R == 8)
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#define PLL_R (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0)
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#else
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#error "PLL configuration: PLL R value is invalid"
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#endif
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#if (CONFIG_CLOCK_PLL_Q == 2)
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#define PLL_Q (0)
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#elif (CONFIG_CLOCK_PLL_Q == 4)
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#define PLL_Q (RCC_PLLCFGR_PLLQ_0)
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#elif (CONFIG_CLOCK_PLL_Q == 6)
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#define PLL_Q (RCC_PLLCFGR_PLLQ_1)
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#elif (CONFIG_CLOCK_PLL_Q == 8)
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#define PLL_Q (RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1)
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#else
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#error "PLL configuration: PLL Q value is invalid"
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#endif
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/* Define MSI range bitfields */
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#if CONFIG_CLOCK_MSI == KHZ(100)
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#define CLOCK_MSIRANGE (0)
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#elif CONFIG_CLOCK_MSI == KHZ(200)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_0)
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#elif CONFIG_CLOCK_MSI == KHZ(400)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_1)
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#elif CONFIG_CLOCK_MSI == KHZ(800)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0)
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#elif CONFIG_CLOCK_MSI == MHZ(1)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_2)
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#elif CONFIG_CLOCK_MSI == MHZ(2)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_0)
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#elif CONFIG_CLOCK_MSI == MHZ(4)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1)
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#elif CONFIG_CLOCK_MSI == MHZ(8)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0)
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#elif CONFIG_CLOCK_MSI == MHZ(16)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_3)
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#elif CONFIG_CLOCK_MSI == MHZ(24)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_0)
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#elif CONFIG_CLOCK_MSI == MHZ(32)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1)
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#elif CONFIG_CLOCK_MSI == MHZ(48)
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#define CLOCK_MSIRANGE (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0)
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#else
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#error "Invalid MSI clock"
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#endif
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/* Configure 48MHz clock source */
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#define CLOCK_PLLQ ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_Q
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#if CLOCK_PLLQ == MHZ(48)
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#define CLOCK48MHZ_USE_PLLQ 1
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#elif CONFIG_CLOCK_MSI == MHZ(48)
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#define CLOCK48MHZ_USE_MSI 1
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#else
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#define CLOCK48MHZ_USE_PLLQ 0
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#define CLOCK48MHZ_USE_MSI 0
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#endif
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#if IS_ACTIVE(CLOCK48MHZ_USE_PLLQ)
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#define CLOCK48MHZ_SELECT (RCC_CCIPR1_CLK48MSEL_1)
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#elif IS_ACTIVE(CLOCK48MHZ_USE_MSI)
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#define CLOCK48MHZ_SELECT (RCC_CCIPR1_CLK48MSEL_1 | RCC_CCIPR1_CLK48MSEL_0)
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#else
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#define CLOCK48MHZ_SELECT (0)
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#endif
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/* Configure the AHB and APB buses prescalers */
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#define CLOCK_AHB_DIV (0)
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#if CONFIG_CLOCK_APB1_DIV == 1
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#define CLOCK_APB1_DIV (0)
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#elif CONFIG_CLOCK_APB1_DIV == 2
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_2)
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#elif CONFIG_CLOCK_APB1_DIV == 4
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0)
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#elif CONFIG_CLOCK_APB1_DIV == 8
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1)
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#elif CONFIG_CLOCK_APB1_DIV == 16
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#define CLOCK_APB1_DIV (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0)
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#endif
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#if CONFIG_CLOCK_APB2_DIV == 1
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#define CLOCK_APB2_DIV (0)
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#elif CONFIG_CLOCK_APB2_DIV == 2
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_2)
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#elif CONFIG_CLOCK_APB2_DIV == 4
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0)
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#elif CONFIG_CLOCK_APB2_DIV == 8
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1)
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#elif CONFIG_CLOCK_APB2_DIV == 16
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#define CLOCK_APB2_DIV (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0)
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#endif
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/* Only periph_hwrng requires 48MHz for the moment */
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#if IS_USED(MODULE_PERIPH_HWRNG)
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#if !IS_ACTIVE(CLOCK48MHZ_USE_PLLQ) && !IS_ACTIVE(CLOCK48MHZ_USE_MSI)
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#error "No 48MHz clock source available, HWRNG cannot work"
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#endif
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#define CLOCK_ENABLE_48MHZ 1
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#else
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#define CLOCK_ENABLE_48MHZ 0
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#endif
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/* Check if PLL is required
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- When used as system clock
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- When PLLQ is used as 48MHz clock source
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || \
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(IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_PLLQ))
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#define CLOCK_ENABLE_PLL 1
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#else
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#define CLOCK_ENABLE_PLL 0
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#endif
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/* Check if HSE is required:
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- When used as system clock
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- When used as PLL input clock
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
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(IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE))
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#define CLOCK_ENABLE_HSE 1
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#else
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#define CLOCK_ENABLE_HSE 0
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#endif
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/* HSE cannot be enabled if not provided by the board */
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#if IS_ACTIVE(CLOCK_ENABLE_HSE) && !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#error "HSE is required by the clock configuration but is not provided by the board."
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#endif
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/* Check if HSI is required:
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- When used as system clock
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- When used as PLL input clock
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
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(IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI))
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#define CLOCK_ENABLE_HSI 1
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#else
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#define CLOCK_ENABLE_HSI 0
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#endif
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/* Check if MSI is required
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- When used as system clock
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- When used as PLL input clock
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*/
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#if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
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(IS_ACTIVE(CLOCK_ENABLE_PLL) && IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)) || \
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(IS_ACTIVE(CLOCK_ENABLE_48MHZ) && IS_ACTIVE(CLOCK48MHZ_USE_MSI))
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#define CLOCK_ENABLE_MSI 1
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#else
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#define CLOCK_ENABLE_MSI 0
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#endif
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/* Deduct the needed flash wait states from the core clock frequency */
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#if CLOCK_AHB <= MHZ(20)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_0WS
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#elif CLOCK_AHB <= MHZ(40)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_1WS
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#elif CLOCK_AHB <= MHZ(60)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_2WS
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#elif CLOCK_AHB <= MHZ(80)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_3WS
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#elif CLOCK_AHB <= MHZ(100)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_4WS
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#elif CLOCK_AHB <= MHZ(110)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_5WS
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#endif
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->CIER = 0;
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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/* use HSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configured by the board */
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RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
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/* configure flash wait states */
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FLASH->ACR = FLASH_WAITSTATES;
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/* disable all active clocks except HSI -> resets the clk configuration */
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RCC->CR = RCC_CR_HSION;
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/* Enable the HSE clock only when it's used */
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if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
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RCC->CR |= (RCC_CR_HSEON);
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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}
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/* Enable the MSI clock only when it's used */
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if (IS_ACTIVE(CLOCK_ENABLE_MSI)) {
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RCC->CR |= (RCC_CR_MSION | CLOCK_MSIRANGE | RCC_CR_MSIRGSEL);
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while (!(RCC->CR & RCC_CR_MSIRDY)) {}
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}
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/* Enable the PLL clock only when it's used */
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if (IS_ACTIVE(CLOCK_ENABLE_PLL)) {
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if (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI) && IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) {
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/* configure the low speed clock domain */
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stmclk_enable_lfclk();
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/* now we can enable the MSI PLL mode to enhance accuracy of the MSI */
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RCC->CR |= RCC_CR_MSIPLLEN;
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while (!(RCC->CR & RCC_CR_MSIRDY)) {}
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}
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/* configure and start the PLL */
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RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | PLL_Q);
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if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
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/* Enable PLLCLK if PLL is used as system clock */
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN;
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}
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if (IS_ACTIVE(CLOCK48MHZ_USE_PLLQ)) {
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/* Enable PLLQ if PLL is used as 48MHz source clock */
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLQEN;
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}
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RCC->CR |= (RCC_CR_PLLON);
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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}
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/* Configure SYSCLK */
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if (!IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) {
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RCC->CFGR &= ~RCC_CFGR_SW;
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}
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if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
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/* Select HSE as system clock */
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RCC->CFGR |= RCC_CFGR_SW_HSE;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
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}
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else if (IS_ACTIVE(CONFIG_USE_CLOCK_MSI)) {
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/* Select MSI as system clock */
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RCC->CFGR |= RCC_CFGR_SW_MSI;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) {}
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}
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else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
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if (CLOCK_AHB > MHZ(80)) {
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/* Divide HCLK by 2 before enabling the PLL */
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RCC->CFGR |= RCC_CFGR_HPRE_3;
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}
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/* Select main PLL as system clock */
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
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if (CLOCK_AHB > MHZ(80)) {
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/* Wait 1us before switching back to full speed */
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/* Use volatile to prevent the compiler from optimizing the loop */
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volatile uint8_t count = CLOCK_CORECLOCK / MHZ(1);
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while (count--) {}
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RCC->CFGR &= ~RCC_CFGR_HPRE_3;
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}
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}
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if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
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/* Disable HSI only if not used */
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stmclk_disable_hsi();
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}
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if (IS_ACTIVE(CLOCK_ENABLE_48MHZ)) {
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/* configure the clock used for the 48MHz clock tree (USB, RNG) */
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RCC->CCIPR1 = CLOCK48MHZ_SELECT;
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}
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irq_restore(is);
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}
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