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97 lines
4.4 KiB
Plaintext
97 lines
4.4 KiB
Plaintext
/**
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@defgroup cpu_stm32 STM32
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@ingroup cpu
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@brief All STM32 families code and definitions
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This module contains the code and definitions for STM32 cpu
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families supported by RIOT: F0, F1, F2, F3, F4, F7, G0, G4, L0, L1, L4, L5 and WB.
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All constants described below can be configured using `CFLAGS` from the command
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line or in the application Makefile.
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Clock configuration
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===================
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All STM32 cpus have clock configuration code and macros. It is recommend to read
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the reference manual of the CPU of interest to learn about the corresponding
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clock tree and the possible configurations.
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For all families, different input clock sources are available for the SYSCLK
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system clock (but only one can be used at a time):
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- HSE (High Speed External): HSE depends on the board configuration and its
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presence is specified by the `CONFIG_BOARD_HAS_HSE` constant at board level.
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The `CONFIG_CLOCK_HSE` constant specifies the frequency of the external oscillator
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in Hz.
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To use HSE as system clock (SYSCLK), set `CONFIG_USE_CLOCK_HSE` constant to 1;
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- HSI (High Speed Internal): HSI is either 8MHz or 16MHz, depending
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on the families.
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To use HSI as system clock (SYSCLK), set `CONFIG_USE_CLOCK_HSI` constant to 1;
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- MSI (Multi-Speed Internal): This internal oscillator is only available on L0,
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L1, L4, L5 and WB families.
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To use MSI as system clock (SYSCLK), set `CONFIG_USE_CLOCK_MSI` constant to 1
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The MSI clock frequency can be configured using the `CONFIG_CLOCK_MSI`
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constant (in Hz);
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- PLL (Phase-Locked Loop) provides a finely configurable clock source for
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SYSCLK and allows to reach precise and high clock speeds, depending on the
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input source. In RIOT, this is the default clock source for SYSCLK.
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To use the PLL as system clock (SYSCLK), set `CONFIG_USE_CLOCK_PLL` constant
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to 1 (default).
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If an HSE is provided by the board, it is automatically selected as input
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source for the PLL, otherwise HSI is selected.
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On L4 and WB, the PLL input source can be selected between HSE, HSI and MSI
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(default): to configure the PLL input source, just set
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`CONFIG_CLOCK_PLL_SRC_HSI`, `CONFIG_CLOCK_PLL_SRC_HSE` or
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`CONFIG_CLOCK_PLL_SRC_MSI` to 1.
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2 types of PLL are available on STM32:
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- for stm32f[2|4|7], stm32g[0|4] and stm32[l4|l5|wb], the PLL can be
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configured with several parameters M, N, P, Q and R (optional). M is the
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input divider, N is the multiplier and P, Q and R are output dividers.
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On stm32f[2|4|7], the clock source from the P output divider is used as
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SYSCLK input, the clock source from the Q output divider can be used as
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48MHz.
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On stm32g[0|4] and stm32[l4|l5|wb], the clock source from the R output
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divider is used as SYSCLK input.
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Constants used to configure the PLL on these families are
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`CONFIG_CLOCK_PLL_M`, `CONFIG_CLOCK_PLL_N`, `CONFIG_CLOCK_PLL_P`,
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`CONFIG_CLOCK_PLL_Q` and `CONFIG_CLOCK_PLL_R`.
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- for stm32f[0|1|3] and stm32l[0|1], the PLL can be configured with a
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predivider parameter and a multiplier parameter.
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Constants used to configure the PLL on these families are
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`CONFIG_CLOCK_PLL_DIV` (l0, l1) or `CONFIG_CLOCK_PLL_PREDIV` (f0, f1, f3)
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and `CONFIG_CLOCK_PLL_MUL`.
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Advanced Peripheral Bus (APB) clock prescalers:
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-----------------------------------------------
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These prescalers are used to compute the PCLK1 and PCLK2 clock values.
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Use `CONFIG_CLOCK_APB1_DIV` and `CONFIG_CLOCK_APB2_DIV` constants to configure
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the prescalers (just set the frequency factor).
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APB2 is not available on f0 and g0 families so setting `CONFIG_CLOCK_APB2_DIV`
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will have no effect on them.
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MCO (Microcontroller Clock Output) parameters:
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----------------------------------------------
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For stm32f[2|4|7], clock outputs can be configured as follows:
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- set `CONFIG_CLOCK_ENABLE_MCO1` to enable MCO1 (on PA8) and use
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`CONFIG_CLOCK_MCO1_PRE` constant to specify the MCO1 prescaler (default to 1).
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Possible sources are HSE, HSI and PLL (the default): set 1 to
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`CONFIG_CLOCK_MCO1_USE_HSE`, `CONFIG_CLOCK_MCO1_USE_HSI` or
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`CONFIG_CLOCK_MCO1_USE_PLL` to select the source;
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- set `CONFIG_CLOCK_ENABLE_MCO2` to enable MCO1 (on PC9) and use
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`CONFIG_CLOCK_MCO2_PRE` constant to specify the MCO2 prescaler (default to 1).
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Possible sources are HSE, SYSCLK, PLLI2S and PLL (the default): set 1 to
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`CONFIG_CLOCK_MCO1_USE_HSE`, `CONFIG_CLOCK_MCO1_USE_SYSCLK`,
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`CONFIG_CLOCK_MCO1_USE_PLLI2S` or `CONFIG_CLOCK_MCO1_USE_PLL` to select the
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source;
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*/
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