mirror of
https://github.com/RIOT-OS/RIOT.git
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bf96c28889
Generated new vendor header files from upstream SVD files using:
./SVDConv "$PICO_SDK_DIR"/src/rp2040/hardware_regs/rp2040.svd \
--generate=header --fields=macro --fields=enum
Note: The missing `--fields=struct` flag resulted in the header no
longer containing bit-fields to represent different fields
within registers. While this would generally ease writing code,
the RP2040 has the unpleasant feature of corrupting the
remaining bits of the register when a write access that is not
word-sized occurs in the memory mapped I/O area. This could
happen e.g. when a bit field is byte-sized and byte-aligned.
119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
/*
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* Copyright (C) 2021 Otto-von-Guericke Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_rpx0xx
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* @{
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*
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* @file
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* @brief Implementation of the phase locked loop (PLL)
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* to drive the ROSC or XOSC to a higher frequency
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*
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* @author Fabian Hüßler <fabian.huessler@ovgu.de>
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*
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* @}
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*/
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#include <assert.h>
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#include "macros/units.h"
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#include "periph_cpu.h"
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#include "vendor/RP2040.h"
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#include "io_reg.h"
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/**
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* @brief Start the PLL for the system clock (@p pll = PLL_SYS) or
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* the USB clock (@p pll = PLL_USB)
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*/
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static void _pll_start(PLL_SYS_Type *pll, uint8_t ref_div,
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uint16_t vco_feedback_scale,
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uint8_t post_div_1, uint8_t post_div_2)
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{
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assert(PLL_REF_DIV_MIN <= ref_div);
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assert(ref_div <= PLL_REF_DIV_MAX);
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assert(PLL_VCO_FEEDBACK_SCALE_MIN <= vco_feedback_scale);
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assert(vco_feedback_scale <= PLL_VCO_FEEDBACK_SCALE_MAX);
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assert(PLL_POSTDIV_MIN <= post_div_1);
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assert(post_div_1 <= PLL_POSTDIV_MAX);
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assert(PLL_POSTDIV_MIN <= post_div_2);
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assert(post_div_2 <= PLL_POSTDIV_MAX);
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/* program reference clock divider */
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io_reg_write_dont_corrupt(&pll->CS, ref_div << PLL_SYS_CS_REFDIV_Pos,
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PLL_SYS_CS_REFDIV_Msk);
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/* program feedback divider */
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io_reg_write_dont_corrupt(&pll->FBDIV_INT,
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vco_feedback_scale << PLL_SYS_FBDIV_INT_FBDIV_INT_Pos,
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PLL_SYS_FBDIV_INT_FBDIV_INT_Msk);
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/* turn on the main power */
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io_reg_atomic_clear(&pll->PWR, (1U << PLL_SYS_PWR_VCOPD_Pos)
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| (1U << PLL_SYS_PWR_DSMPD_Pos)
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| (1U << PLL_SYS_PWR_PD_Pos));
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/* wait for VCO to lock (i.e. keep its output stable) */
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while (!(pll->CS & PLL_SYS_CS_LOCK_Msk)) { }
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/* set up post divisors and turn them on */
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pll->PRIM = (post_div_1 << PLL_SYS_PRIM_POSTDIV1_Pos)
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| (post_div_2 << PLL_SYS_PRIM_POSTDIV2_Pos);
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io_reg_atomic_clear(&pll->PWR, 1U << PLL_SYS_PWR_POSTDIVPD_Pos);
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}
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/**
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* @brief Stop the PLL for the system clock (@p pll = PLL_SYS) or
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* the USB clock (@p pll = PLL_USB)
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*/
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static void _pll_stop(PLL_SYS_Type *pll)
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{
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uint32_t reg = (1U << PLL_SYS_PWR_VCOPD_Pos)
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| (1U << PLL_SYS_PWR_POSTDIVPD_Pos)
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| (1U << PLL_SYS_PWR_DSMPD_Pos)
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| (1U << PLL_SYS_PWR_PD_Pos);
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io_reg_atomic_set(&pll->PWR, reg);
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}
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void pll_start_sys(uint8_t ref_div,
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uint16_t vco_feedback_scale,
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uint8_t post_div_1, uint8_t post_div_2)
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{
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_pll_start(PLL_SYS, ref_div, vco_feedback_scale, post_div_1, post_div_2);
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}
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void pll_start_usb(uint8_t ref_div,
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uint16_t vco_feedback_scale,
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uint8_t post_div_1, uint8_t post_div_2)
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{
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_pll_start(PLL_USB, ref_div, vco_feedback_scale, post_div_1, post_div_2);
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}
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void pll_stop_sys(void)
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{
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_pll_stop(PLL_SYS);
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}
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void pll_stop_usb(void)
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{
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_pll_stop(PLL_USB);
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}
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/**
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* @brief Reset the PLL of the system clock
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*/
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void pll_reset_sys(void)
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{
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periph_reset(1U << RESETS_RESET_pll_sys_Pos);
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periph_reset_done(1U << RESETS_RESET_pll_sys_Pos);
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}
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/**
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* @brief Reset the PLL of the USB clock
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*/
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void pll_reset_usb(void)
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{
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periph_reset(1U << RESETS_RESET_pll_usb_Pos);
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periph_reset_done(1U << RESETS_RESET_pll_usb_Pos);
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}
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