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cde8ac6093
The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB, Bluetooth Low Energy and in some variants NFC. This patch implements the first steps for having support for this CPU. While the QN908x can be considered the successor of similar chips from NXP like the KW41Z when looking at the feature set, the internal architecture, boot image format and CPU peripherals don't match those in the Kinetis line. Therefore, this patch creates a new directory for just the QN908x chip under cpu/qn908x. The minimal set of peripherals are implemented in this patch to allow the device to boot and enable a GPIO: the gpio and wdt peripheral modules only. The wdt driver is required to boot and disable the wdt. On reset, the wdt is disabled by the chip, however the QN908x bootloader stored in the internal ROM enables the wdt and sets a timer to reboot after 10 seconds, therefore it is needed to disable the wdt in RIOT OS soon after booting. This patch sets it up such that when no periph_wdt module is used the Watchdog is disabled, but if the periph_wdt is used it must be configured (initialized) within the first 10 seconds. Tests performed: Defined a custom board for this CPU and compiled a simple application that blinks some LEDs. Manually tested with periph_wdt and with periph_wdt_cb as well.
130 lines
4.0 KiB
C
130 lines
4.0 KiB
C
/*
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* Copyright (C) 2020 iosabi
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_qn908x
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* @{
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*
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* @file
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* @brief Default interrupt service routine definitions for NXP QN908x
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*
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* These weak default definitions act as a fallback definition if no driver
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* defines a ISR for the specific interrupt.
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*
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* @author iosabi <iosabi@protonmail.com>
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*
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* @}
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*/
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#include "cpu.h"
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#include "vectors_cortexm.h"
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#include "vectors_qn908x.h"
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/* These are defined in vectors_cortexm.c. */
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extern void reset_handler_default(void);
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extern uint32_t _estack; /* Exception stack pointer. */
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/**
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* @brief Jump to the reset_handle_default handler with the exception stack.
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*/
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__attribute__((noreturn)) static inline void cpu_restart(void)
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{
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/* Reset the stack pointer to the beginning again and jump to the reset
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* handler at the expected address.
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*/
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__asm volatile ("msr msp, %[estack]\n"
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"mov pc, %[entry]\n"
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:
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: [ estack ] "r" (&_estack),
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[ entry ] "r" (reset_handler_default)
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: "memory");
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/* This function doesn't return anyway. */
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while (1) {}
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}
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/**
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* @brief Remap the flash to address 0 on start.
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*
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* The bootloader will jump to the flash at address 0x21000000 which is aliased
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* to the flash on this CPU. However, our program is linked to run as if the
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* flash is mapped at address 0 which is the common case. The range starting at
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* address 0 can be mapped to flash, RAM or ROM via the SYS_MODE_CTRL register,
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* but on reset the default value (0x0) means that it is mapped to ROM.
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* We need to remap the flash and change the program counter to be running from
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* the right address range (0).
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*/
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void pre_startup(void)
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{
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register unsigned int pc;
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/* Disable interrupts */
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__disable_irq();
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/* Check whether we are running from the 0x21000000 range. If that's the
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* case we need to remap the flash to the address 0 in SYS_MODE_CTRL and
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* jump back to the reset_handler_default so everything starts as running
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* from the address 0x0 instead.
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*/
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__asm volatile ("mov %0, pc" : "=r" (pc));
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if ((pc & 0x21000000) == 0x21000000) {
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SYSCON->SYS_MODE_CTRL |= 1;
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cpu_restart();
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}
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}
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/* QN908x interrupt service routines */
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WEAK_DEFAULT void isr_ext_gpio_wakeup(void);
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WEAK_DEFAULT void isr_osc(void);
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WEAK_DEFAULT void isr_acmp0(void);
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WEAK_DEFAULT void isr_acmp1(void);
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WEAK_DEFAULT void isr_rtc_sec(void);
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WEAK_DEFAULT void isr_rtc_fr(void);
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WEAK_DEFAULT void isr_cs_wakeup(void);
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WEAK_DEFAULT void isr_cs(void);
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WEAK_DEFAULT void isr_gpioa(void);
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WEAK_DEFAULT void isr_gpiob(void);
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WEAK_DEFAULT void isr_dma0(void);
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WEAK_DEFAULT void isr_pin_int0(void);
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WEAK_DEFAULT void isr_pin_int1(void);
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WEAK_DEFAULT void isr_pin_int2(void);
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WEAK_DEFAULT void isr_pin_int3(void);
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WEAK_DEFAULT void isr_osc_int_low(void);
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WEAK_DEFAULT void isr_usb0(void);
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WEAK_DEFAULT void isr_flexcomm0(void);
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WEAK_DEFAULT void isr_flexcomm1(void);
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WEAK_DEFAULT void isr_flexcomm2(void);
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WEAK_DEFAULT void isr_flexcomm3(void);
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WEAK_DEFAULT void isr_ble(void);
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WEAK_DEFAULT void isr_fsp(void);
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WEAK_DEFAULT void isr_qdec0(void);
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WEAK_DEFAULT void isr_qdec1(void);
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WEAK_DEFAULT void isr_ctimer0(void);
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WEAK_DEFAULT void isr_ctimer1(void);
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WEAK_DEFAULT void isr_ctimer2(void);
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WEAK_DEFAULT void isr_ctimer3(void);
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WEAK_DEFAULT void isr_wdt(void);
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WEAK_DEFAULT void isr_adc(void);
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WEAK_DEFAULT void isr_dac(void);
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WEAK_DEFAULT void isr_xtal_ready(void);
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WEAK_DEFAULT void isr_flash(void);
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WEAK_DEFAULT void isr_spifi0(void);
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WEAK_DEFAULT void isr_sct0(void);
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WEAK_DEFAULT void isr_rng(void);
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WEAK_DEFAULT void isr_calib(void);
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WEAK_DEFAULT void isr_ble_tx(void);
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WEAK_DEFAULT void isr_ble_rx(void);
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WEAK_DEFAULT void isr_ble_freq_hop(void);
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WEAK_DEFAULT void isr_bod(void);
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void dummy_handler(void)
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{
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dummy_handler_default();
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}
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