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cde8ac6093
The NXP QN908x CPU family is a Cortex-M4F CPU with integrated USB, Bluetooth Low Energy and in some variants NFC. This patch implements the first steps for having support for this CPU. While the QN908x can be considered the successor of similar chips from NXP like the KW41Z when looking at the feature set, the internal architecture, boot image format and CPU peripherals don't match those in the Kinetis line. Therefore, this patch creates a new directory for just the QN908x chip under cpu/qn908x. The minimal set of peripherals are implemented in this patch to allow the device to boot and enable a GPIO: the gpio and wdt peripheral modules only. The wdt driver is required to boot and disable the wdt. On reset, the wdt is disabled by the chip, however the QN908x bootloader stored in the internal ROM enables the wdt and sets a timer to reboot after 10 seconds, therefore it is needed to disable the wdt in RIOT OS soon after booting. This patch sets it up such that when no periph_wdt module is used the Watchdog is disabled, but if the periph_wdt is used it must be configured (initialized) within the first 10 seconds. Tests performed: Defined a custom board for this CPU and compiled a simple application that blinks some LEDs. Manually tested with periph_wdt and with periph_wdt_cb as well.
119 lines
3.8 KiB
C
119 lines
3.8 KiB
C
/*
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* Copyright (C) 2020 iosabi
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_qn908x
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* @{
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*
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* @file
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* @brief Interrupt service routine declarations NXP QN908x MCUs
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*
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* @author iosabi <iosabi@protonmail.com>
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*
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* @}
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*/
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#ifndef VECTORS_QN908X_H
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#define VECTORS_QN908X_H
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#include <stdint.h>
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#include "vectors_cortexm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Dummy handler
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*/
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void dummy_handler(void);
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/* Device specific interrupt vectors */
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void isr_ext_gpio_wakeup(void); /**< Ext GPIO wakeup */
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void isr_osc(void); /**< BLE wakeup */
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void isr_acmp0(void); /**< Analog comparator0 */
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void isr_acmp1(void); /**< Analog comparator1 */
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void isr_rtc_sec(void); /**< RTC second */
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void isr_rtc_fr(void); /**< RTC free running */
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void isr_cs_wakeup(void); /**< Capacitive sense wakeup */
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void isr_cs(void); /**< Capacitive sense */
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void isr_gpioa(void); /**< GPIO group A */
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void isr_gpiob(void); /**< GPIO group B */
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void isr_dma0(void); /**< DMA controller */
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void isr_pin_int0(void); /**< pin or pattern match engine slice 0 */
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void isr_pin_int1(void); /**< pin or pattern match engine slice 1 */
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void isr_pin_int2(void); /**< pin or pattern match engine slice 2 */
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void isr_pin_int3(void); /**< pin or pattern match engine slice 3 */
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void isr_osc_int_low(void); /**< Inverse of OSC */
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void isr_usb0(void); /**< USB device */
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void isr_flexcomm0(void); /**< Flexcomm Interface 0 (USART) */
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void isr_flexcomm1(void); /**< Flexcomm Interface 1 (USART, I2C) */
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void isr_flexcomm2(void); /**< Flexcomm Interface 2 (SPI, I2C) */
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void isr_flexcomm3(void); /**< Flexcomm Interface 3 (SPI) */
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void isr_ble(void); /**< BLE interrupts */
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void isr_fsp(void); /**< FSP */
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void isr_qdec0(void); /**< QDEC0 */
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void isr_qdec1(void); /**< QDEC1 */
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void isr_ctimer0(void); /**< Standard counter/timer CTIMER0 */
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void isr_ctimer1(void); /**< Standard counter/timer CTIMER1 */
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void isr_ctimer2(void); /**< Standard counter/timer CTIMER2 */
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void isr_ctimer3(void); /**< Standard counter/timer CTIMER3 */
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void isr_wdt(void); /**< Watch dog timer */
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void isr_adc(void); /**< ADC */
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void isr_dac(void); /**< DAC */
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void isr_xtal_ready(void); /**< High frequency crystal ready */
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void isr_flash(void); /**< Flash */
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void isr_spifi0(void); /**< SPI flash interface */
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void isr_sct0(void); /**< SCTimer/PWM */
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void isr_rng(void); /**< Random number generator */
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void isr_calib(void); /**< Calibration */
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void isr_ble_tx(void); /**< ble tx flag */
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void isr_ble_rx(void); /**< ble rx flag */
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void isr_ble_freq_hop(void); /**< ble frequency hop */
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void isr_bod(void); /**< Brown out detect */
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/**
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* @{
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* @brief In-System Programming configuration field
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*
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* After the interrupt vectors, at address 0x110 there's a ISP
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* (In-System Programming) configuration field. Define isp_configuration to
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* any | combination of the following `QN908X_ISP_*` values to change the ISP
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* allowed options.
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*/
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__attribute__((section(".vectors.100")))
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extern const uint32_t isp_configuration;
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/**
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* @brief SMART write enabled to ISP
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*/
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#define QN908X_ISP_SMART_EN 0x80
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/**
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* @brief SMART USB disabled to ISP
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*/
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#define QN908X_ISP_USB_DIS 0x20
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/**
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* @brief SMART UART disabled to ISP
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*/
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#define QN908X_ISP_UART_DIS 0x08
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/**
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* @brief SMART SPI disabled to ISP
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*/
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#define QN908X_ISP_SPI_DIS 0x02
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/** @} */
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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#endif /* VECTORS_QN908X_H */
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