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https://github.com/RIOT-OS/RIOT.git
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dfdd076125
This patch implements the basic support the last of the FLEXCOMM modes, Serial Peripheral Interface, in a simple blocking mode with busy wait, which is enough to test all the SPI functionality end-to-end. Tested reading and writing registers on a SPI peripheral, and checked with the oscilloscope that the frequencies were as expected. Results from `tests/periph_spi`: ``` > init 0 0 2 -1 0 SPI_DEV(0) initialized: mode: 0, clk: 2, cs_port: -1, cs_pin: 0 > bench 1 - write 1000 times 1 byte: 16002 16009 2 - write 1000 times 2 byte: 18001 18008 3 - write 1000 times 100 byte: 802000 802007 4 - write 1000 times 1 byte to register: 24003 24010 5 - write 1000 times 2 byte to register: 26001 26008 6 - write 1000 times 100 byte to register: 810001 810008 7 - read 1000 times 2 byte: 23003 23009 8 - read 1000 times 100 byte: 807002 807009 9 - read 1000 times 2 byte from register: 32002 32009 10 - read 1000 times 100 byte from register: 816002 816009 11 - transfer 1000 times 2 byte: 23003 23009 12 - transfer 1000 times 100 byte: 807003 807010 13 - transfer 1000 times 2 byte to register: 32003 32009 14 - transfer 1000 times 100 byte to register:816002 816009 15 - acquire/release 1000 times: 7222 7228 -- - SUM: 5059250 5059351 ```
82 lines
1.9 KiB
C
82 lines
1.9 KiB
C
/*
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* Copyright (C) 2020 iosabi
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_qn908x
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*
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* @{
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*
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* @file
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* @brief Common Pin MUX functions.
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*
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* The pins in this CPU are multiplexed to several different function. This
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* module allows to configure the pin multiplexer (MUX) from peripheral drivers.
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*
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* @author iosabi <iosabi@protonmail.com>
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*/
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#ifndef GPIO_MUX_H
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#define GPIO_MUX_H
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#include <stdint.h>
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Obtain the GPIO_BASE address from a GPIO_PIN(x, y) value.
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*/
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#define GPIO_T_ADDR_BASE(pin) (GPIOA_BASE + ((pin) & 0xf000u))
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/**
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* @brief Obtain the GPIO_BASE GPIO_Type* pointer from a GPIO_PIN(x, y) value.
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*/
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#define GPIO_T_ADDR(pin) ((GPIO_Type *)(GPIO_T_ADDR_BASE(pin)))
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/**
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* @brief Obtain the "x" port number (0 based) from a GPIO_PIN(x, y) value.
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*
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* This macro needs to be kept in sync with the definition of GPIO_PIN.
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*/
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#define GPIO_T_PORT(pin) ((gpio_t)(pin) >> 12u)
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/**
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* @brief Obtain the pin number "y" from a GPIO_PIN(x, y) value.
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*/
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#define GPIO_T_PIN(pin) ((pin) & 0x00ffu)
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#if defined(GPIOB_BASE) && (GPIO_T_ADDR_BASE(GPIO_PIN(1, 1)) != GPIOB_BASE)
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#error "GPIO_T_ADDR(GPIO_PIN(1, x)) must be the GPIOB address"
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#endif
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/**
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* @brief Return whether the given pin is a CSHW pin.
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*/
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#define GPIO_T_IS_HWCS(pin) (((pin) & 0xff00u) == 0x8000)
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/**
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* @brief Return the given CSHW number from the gpio_t pin.
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*/
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#define GPIO_T_HWCS(pin) ((pin) & 0x0003u)
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/**
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* @brief Configure the pin mux to the given function.
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*
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* The meaning of the function value will depend on the gpio pin.
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*/
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void gpio_init_mux(gpio_t pin, uint32_t func);
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_MUX_H */
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/** @} */
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