mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
edb890ff93
Found and fixed the issue for the kinetis-based boards: The kinetis code is using some macros to map some IRQ names, that differ in some versions of vendor headers, to a RIOT wide unique name. The doxygen of this mapping states, that this mapping must be done before any vendor header is included. Unfortunately, the mapping was so far placed in cpu/kinetis/vectors.c, before any other include statement. In some cases, the vendor headers might be included before the mapping macros in vectors.c, leading to the compilation errors down the line. To fix this, the adaption defines are moved into cpu/kinetis/cpu_conf.h, which is the file that actually includes the vendor headers. This way it is ensured, that these adaption macros are always defined before any vendor header is included, and therefore preventing this kind of error for good.
416 lines
15 KiB
C
416 lines
15 KiB
C
/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_kinetis
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* @{
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*
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* @file
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*
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* @brief Interrupt vector for Kinetis MCUs
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*
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* @note It is not necessary to modify this file to define custom interrupt
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* service routines. All symbols are defined weak, it is only necessary to
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* define a function with the same name in another file to override the default
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* interrupt handlers.
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*/
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/**
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* @name Interrupt vector definition
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* @{
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*/
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#include "vectors_kinetis.h"
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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#ifdef DMA0
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/* Devices with >16 DMA channels combine two channels per IRQ number */
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#if defined(DMA_INT_INT16_MASK)
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[DMA0_DMA16_IRQn ] = isr_dma0_dma16, /* DMA Channel 0, 16 Transfer Complete */
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#elif defined(DMA_INT_INT0_MASK)
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[DMA0_IRQn ] = isr_dma0, /* DMA Channel 0 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT17_MASK)
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[DMA1_DMA17_IRQn ] = isr_dma1_dma17, /* DMA Channel 1, 17 Transfer Complete */
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#elif defined(DMA_INT_INT1_MASK)
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[DMA1_IRQn ] = isr_dma1, /* DMA Channel 1 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT18_MASK)
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[DMA2_DMA18_IRQn ] = isr_dma2_dma18, /* DMA Channel 2, 18 Transfer Complete */
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#elif defined(DMA_INT_INT2_MASK)
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[DMA2_IRQn ] = isr_dma2, /* DMA Channel 2 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT19_MASK)
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[DMA3_DMA19_IRQn ] = isr_dma3_dma19, /* DMA Channel 3, 19 Transfer Complete */
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#elif defined(DMA_INT_INT3_MASK)
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[DMA3_IRQn ] = isr_dma3, /* DMA Channel 3 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT20_MASK)
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[DMA4_DMA20_IRQn ] = isr_dma4_dma20, /* DMA Channel 4, 20 Transfer Complete */
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#elif defined(DMA_INT_INT4_MASK)
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[DMA4_IRQn ] = isr_dma4, /* DMA Channel 4 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT21_MASK)
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[DMA5_DMA21_IRQn ] = isr_dma5_dma21, /* DMA Channel 5, 21 Transfer Complete */
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#elif defined(DMA_INT_INT5_MASK)
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[DMA5_IRQn ] = isr_dma5, /* DMA Channel 5 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT22_MASK)
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[DMA6_DMA22_IRQn ] = isr_dma6_dma22, /* DMA Channel 6, 22 Transfer Complete */
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#elif defined(DMA_INT_INT6_MASK)
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[DMA6_IRQn ] = isr_dma6, /* DMA Channel 6 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT23_MASK)
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[DMA7_DMA23_IRQn ] = isr_dma7_dma23, /* DMA Channel 7, 23 Transfer Complete */
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#elif defined(DMA_INT_INT7_MASK)
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[DMA7_IRQn ] = isr_dma7, /* DMA Channel 7 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT24_MASK)
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[DMA8_DMA24_IRQn ] = isr_dma8_dma24, /* DMA Channel 8, 24 Transfer Complete */
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#elif defined(DMA_INT_INT8_MASK)
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[DMA8_IRQn ] = isr_dma8, /* DMA Channel 8 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT25_MASK)
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[DMA9_DMA25_IRQn ] = isr_dma9_dma25, /* DMA Channel 9, 25 Transfer Complete */
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#elif defined(DMA_INT_INT9_MASK)
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[DMA9_IRQn ] = isr_dma9, /* DMA Channel 9 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT26_MASK)
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[DMA10_DMA26_IRQn] = isr_dma10_dma26, /* DMA Channel 10, 26 Transfer Complete */
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#elif defined(DMA_INT_INT10_MASK)
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[DMA10_IRQn ] = isr_dma10, /* DMA Channel 10 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT27_MASK)
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[DMA11_DMA27_IRQn] = isr_dma11_dma27, /* DMA Channel 11, 27 Transfer Complete */
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#elif defined(DMA_INT_INT11_MASK)
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[DMA11_IRQn ] = isr_dma11, /* DMA Channel 11 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT28_MASK)
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[DMA12_DMA28_IRQn] = isr_dma12_dma28, /* DMA Channel 12, 28 Transfer Complete */
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#elif defined(DMA_INT_INT12_MASK)
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[DMA12_IRQn ] = isr_dma12, /* DMA Channel 12 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT29_MASK)
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[DMA13_DMA29_IRQn] = isr_dma13_dma29, /* DMA Channel 13, 29 Transfer Complete */
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#elif defined(DMA_INT_INT13_MASK)
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[DMA13_IRQn ] = isr_dma13, /* DMA Channel 13 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT30_MASK)
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[DMA14_DMA30_IRQn] = isr_dma14_dma30, /* DMA Channel 14, 30 Transfer Complete */
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#elif defined(DMA_INT_INT14_MASK)
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[DMA14_IRQn ] = isr_dma14, /* DMA Channel 14 Transfer Complete */
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#endif
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#if defined(DMA_INT_INT31_MASK)
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[DMA15_DMA31_IRQn] = isr_dma15_dma31, /* DMA Channel 15, 31 Transfer Complete */
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#elif defined(DMA_INT_INT15_MASK)
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[DMA15_IRQn ] = isr_dma15, /* DMA Channel 15 Transfer Complete */
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#endif
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#ifndef KINETIS_CORE_Z
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[DMA_Error_IRQn ] = isr_dma_error, /* DMA Error Interrupt */
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#endif
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#endif /* defined(DMA0) */
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#if defined(MCM) && !defined(KINETIS_CORE_Z)
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[MCM_IRQn ] = isr_mcm, /* Normal Interrupt */
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#endif
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#if defined(FTFA)
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[FTFA_IRQn ] = isr_ftfa, /* FTFA command complete */
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#ifndef KINETIS_CORE_Z
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[FTFA_Collision_IRQn] = isr_ftfa_collision, /* FTFA read collision */
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#endif
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#elif defined(FTFE)
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[FTFE_IRQn ] = isr_ftfe, /* FTFE command complete */
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#ifndef KINETIS_CORE_Z
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[FTFE_Collision_IRQn] = isr_ftfe_collision, /* FTFE read collision */
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#endif
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#elif defined(FTFL)
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[FTFL_IRQn ] = isr_ftfl, /* FTFL command complete */
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#ifndef KINETIS_CORE_Z
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[FTFL_Collision_IRQn] = isr_ftfl_collision, /* FTFL read collision */
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#endif
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#endif
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#ifdef PMC
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[LVD_LVW_IRQn ] = isr_lvd_lvw, /* Low Voltage Detect, Low Voltage Warning */
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#endif
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#ifdef LLWU
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[LLWU_IRQn ] = isr_llwu, /* Low Leakage Wakeup Unit */
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#endif
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#ifdef WDOG
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[WDOG_EWM_IRQn ] = isr_wdog_ewm, /* WDOG/EWM Interrupt */
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#endif
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#ifdef RNG
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[RNG_IRQn ] = isr_rng, /* RNG Interrupt */
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#endif
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#ifdef I2C0
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[I2C0_IRQn ] = isr_i2c0, /* I2C0 interrupt */
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#endif
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#ifdef I2C1
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[I2C1_IRQn ] = isr_i2c1, /* I2C1 interrupt */
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#endif
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#ifdef I2C2
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[I2C2_IRQn ] = isr_i2c2, /* I2C2 interrupt */
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#endif
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#ifdef I2C3
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[I2C3_IRQn ] = isr_i2c3, /* I2C3 interrupt */
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#endif
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#ifdef SPI0
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[SPI0_IRQn ] = isr_spi0, /* SPI0 Interrupt */
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#endif
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#ifdef SPI1
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[SPI1_IRQn ] = isr_spi1, /* SPI1 Interrupt */
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#endif
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#ifdef SPI2
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[SPI2_IRQn ] = isr_spi2, /* SPI2 Interrupt */
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#endif
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#ifdef I2S0
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#ifdef I2S_TCR1_TFW_MASK
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/* K parts */
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[I2S0_Tx_IRQn ] = isr_i2s0_tx, /* I2S0 transmit interrupt */
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[I2S0_Rx_IRQn ] = isr_i2s0_rx, /* I2S0 receive interrupt */
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#else
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/* KL parts */
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[I2S0_IRQn ] = isr_i2s0, /* I2S0 interrupt */
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#endif
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#endif
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#ifdef UART0
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#ifdef KINETIS_SINGLE_UART_IRQ
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[UART0_IRQn] = isr_uart0, /* UART0 interrupt */
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#else
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#ifdef UART_RPL_RPL_MASK
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[UART0_LON_IRQn ] = isr_uart0_lon, /* UART0 LON interrupt */
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#endif
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[UART0_RX_TX_IRQn] = isr_uart0_rx_tx, /* UART0 Receive/Transmit interrupt */
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[UART0_ERR_IRQn ] = isr_uart0_err, /* UART0 Error interrupt */
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#endif
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#endif
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#ifdef UART1
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#ifdef KINETIS_SINGLE_UART_IRQ
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[UART1_IRQn] = isr_uart1, /* UART1 interrupt */
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#else
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[UART1_RX_TX_IRQn] = isr_uart1_rx_tx, /* UART1 Receive/Transmit interrupt */
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[UART1_ERR_IRQn ] = isr_uart1_err, /* UART1 Error interrupt */
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#endif
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#endif
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#ifdef UART2
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#if defined(KINETIS_SINGLE_UART_IRQ)
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[UART2_IRQn] = isr_uart2, /* UART2 interrupt */
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#elif defined(FLEXIO_VERID_MAJOR_MASK)
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/* KL parts with FlexIO uses combined IRQ */
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[UART2_FLEXIO_IRQn] = isr_uart2_flexio, /* UART2 or FLEXIO */
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#else
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[UART2_RX_TX_IRQn] = isr_uart2_rx_tx, /* UART2 Receive/Transmit interrupt */
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[UART2_ERR_IRQn ] = isr_uart2_err, /* UART2 Error interrupt */
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#endif
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#endif
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#ifdef UART3
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#ifdef KINETIS_SINGLE_UART_IRQ
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[UART3_IRQn] = isr_uart3, /* UART3 interrupt */
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#else
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[UART3_RX_TX_IRQn] = isr_uart3_rx_tx, /* UART3 Receive/Transmit interrupt */
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[UART3_ERR_IRQn ] = isr_uart3_err, /* UART3 Error interrupt */
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#endif
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#endif
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#ifdef UART4
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#ifdef KINETIS_SINGLE_UART_IRQ
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[UART4_IRQn] = isr_uart4, /* UART4 interrupt */
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#else
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[UART4_RX_TX_IRQn] = isr_uart4_rx_tx, /* UART4 Receive/Transmit interrupt */
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[UART4_ERR_IRQn ] = isr_uart4_err, /* UART4 Error interrupt */
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#endif
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#endif
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#ifdef UART5
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#ifdef KINETIS_SINGLE_UART_IRQ
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[UART5_IRQn] = isr_uart5, /* UART5 interrupt */
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#else
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[UART5_RX_TX_IRQn] = isr_uart5_rx_tx, /* UART5 Receive/Transmit interrupt */
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[UART5_ERR_IRQn ] = isr_uart5_err, /* UART5 Error interrupt */
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#endif
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#endif
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#ifdef ADC0
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[ADC0_IRQn ] = isr_adc0, /* ADC0 interrupt */
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#endif
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#ifdef ADC1
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[ADC1_IRQn ] = isr_adc1, /* ADC1 interrupt */
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#endif
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#ifdef ADC2
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[ADC2_IRQn ] = isr_adc2, /* ADC2 interrupt */
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#endif
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#ifdef CMP0
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[CMP0_IRQn ] = isr_cmp0, /* CMP0 interrupt */
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#endif
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#ifdef CMP1
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[CMP1_IRQn ] = isr_cmp1, /* CMP1 interrupt */
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#endif
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#ifdef CMP2
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[CMP2_IRQn ] = isr_cmp2, /* CMP2 interrupt */
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#endif
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#ifdef CMP3
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[CMP3_IRQn ] = isr_cmp3, /* CMP3 interrupt */
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#endif
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#ifdef FTM0
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[FTM0_IRQn ] = isr_ftm0, /* FTM0 fault, overflow and channels interrupt */
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#endif
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#ifdef FTM1
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[FTM1_IRQn ] = isr_ftm1, /* FTM1 fault, overflow and channels interrupt */
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#endif
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#ifdef FTM2
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[FTM2_IRQn ] = isr_ftm2, /* FTM2 fault, overflow and channels interrupt */
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#endif
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#ifdef FTM3
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[FTM3_IRQn ] = isr_ftm3, /* FTM3 fault, overflow and channels interrupt */
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#endif
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#ifdef CMT
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[CMT_IRQn ] = isr_cmt, /* CMT interrupt */
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#endif
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#ifdef RTC
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[RTC_IRQn ] = isr_rtc, /* RTC interrupt */
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# ifndef KINETIS_SERIES_EA
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[RTC_Seconds_IRQn] = isr_rtc_seconds, /* RTC seconds interrupt */
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# endif
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#endif
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#ifdef PIT
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#ifdef KINETIS_CORE_Z
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# ifdef KINETIS_SERIES_EA
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[PIT0_IRQn ] = isr_pit0, /* PIT timer channel 0 interrupt */
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[PIT1_IRQn ] = isr_pit1, /* PIT timer channel 1 interrupt */
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# else
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[PIT_IRQn ] = isr_pit, /* PIT any channel interrupt */
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#endif
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#else
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[PIT0_IRQn ] = isr_pit0, /* PIT timer channel 0 interrupt */
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[PIT1_IRQn ] = isr_pit1, /* PIT timer channel 1 interrupt */
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[PIT2_IRQn ] = isr_pit2, /* PIT timer channel 2 interrupt */
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[PIT3_IRQn ] = isr_pit3, /* PIT timer channel 3 interrupt */
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#endif
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#endif /* defined(PIT) */
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#ifdef PDB0
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[PDB0_IRQn ] = isr_pdb0, /* PDB0 Interrupt */
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#endif
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#ifdef USB0
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[USB0_IRQn ] = isr_usb0, /* USB0 interrupt */
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#endif
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#ifdef USBDCD
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[USBDCD_IRQn ] = isr_usbdcd, /* USBDCD Interrupt */
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#endif
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#if DAC0_BASE /* Not #ifdef because of error in MKW2xD.h files */
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[DAC0_IRQn ] = isr_dac0, /* DAC0 interrupt */
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#endif
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#ifdef DAC1
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[DAC1_IRQn ] = isr_dac1, /* DAC1 interrupt */
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#endif
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#ifdef MCG
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#ifndef MCG_MC_LIRC_DIV2_MASK
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/* Only on full MCG, not MCG_Lite */
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[MCG_IRQn ] = isr_mcg, /* MCG Interrupt */
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#endif /* MCG_MC_LIRC_DIV2_MASK */
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#endif /* MCG */
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#ifdef LPTMR0
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[LPTMR0_IRQn ] = isr_lptmr0, /* LPTimer interrupt */
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#endif
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#ifdef PORTA
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[PORTA_IRQn ] = isr_porta, /* Port A interrupt */
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#endif
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#ifdef KINETIS_CORE_Z
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#if defined(PORTB) && defined(PORTC) && !defined(PORTD)
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[PORTB_PORTC_IRQn] = isr_portb_portc, /* Port B, C combined interrupt */
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#elif defined(PORTC) && defined(PORTD)
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[PORTC_PORTD_IRQn] = isr_portc_portd, /* Port C, D combined interrupt */
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#endif
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#else
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#ifdef PORTB
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[PORTB_IRQn ] = isr_portb, /* Port B interrupt */
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#endif
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#ifdef PORTC
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[PORTC_IRQn ] = isr_portc, /* Port C interrupt */
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#endif
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#ifdef PORTD
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[PORTD_IRQn ] = isr_portd, /* Port D interrupt */
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#endif
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#ifdef PORTE
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[PORTE_IRQn ] = isr_porte, /* Port E interrupt */
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#endif
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#endif
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#if __CORTEX_M >= 3
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[SWI_IRQn ] = isr_swi, /* Software interrupt */
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#endif
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#ifdef CAN0
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[CAN0_ORed_Message_buffer_IRQn] = isr_can0_ored_message_buffer, /* CAN0 OR'd message buffers interrupt */
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[CAN0_Bus_Off_IRQn] = isr_can0_bus_off, /* CAN0 bus off interrupt */
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[CAN0_Error_IRQn ] = isr_can0_error, /* CAN0 error interrupt */
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[CAN0_Tx_Warning_IRQn] = isr_can0_tx_warning, /* CAN0 Tx warning interrupt */
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[CAN0_Rx_Warning_IRQn] = isr_can0_rx_warning, /* CAN0 Rx warning interrupt */
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[CAN0_Wake_Up_IRQn] = isr_can0_wake_up, /* CAN0 wake up interrupt */
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#endif
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#ifdef CAN1
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[CAN1_ORed_Message_buffer_IRQn] = isr_can1_ored_message_buffer, /* CAN1 OR'd message buffers interrupt */
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[CAN1_Bus_Off_IRQn] = isr_can1_bus_off, /* CAN1 bus off interrupt */
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[CAN1_Error_IRQn ] = isr_can1_error, /* CAN1 error interrupt */
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[CAN1_Tx_Warning_IRQn] = isr_can1_tx_warning, /* CAN1 Tx warning interrupt */
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[CAN1_Rx_Warning_IRQn] = isr_can1_rx_warning, /* CAN1 Rx warning interrupt */
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[CAN1_Wake_Up_IRQn] = isr_can1_wake_up, /* CAN1 wake up interrupt */
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#endif
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#ifdef MSCAN
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[MSCAN_RX_IRQn] = isr_mscan_rx, /* MSCAN RX interrupt */
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[MSCAN_TX_IRQn] = isr_mscan_tx, /* MSCAN TX/Err/Wake-up interrupt */
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#endif
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#ifdef SDHC
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[SDHC_IRQn ] = isr_sdhc, /* SDHC interrupt */
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#endif
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#ifdef ENET
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[ENET_1588_Timer_IRQn] = isr_enet_1588_timer, /* Ethernet MAC IEEE 1588 Timer Interrupt */
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[ENET_Transmit_IRQn] = isr_enet_transmit, /* Ethernet MAC Transmit Interrupt */
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[ENET_Receive_IRQn] = isr_enet_receive, /* Ethernet MAC Receive Interrupt */
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[ENET_Error_IRQn ] = isr_enet_error, /* Ethernet MAC Error and miscellaneous Interrupt */
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#endif
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#ifdef LPUART0
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[LPUART0_IRQn ] = isr_lpuart0, /* LPUART0 status/error interrupt */
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#endif
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#ifdef LPUART1
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[LPUART1_IRQn ] = isr_lpuart1, /* LPUART1 status/error interrupt */
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#endif
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#ifdef LPUART2
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[LPUART2_IRQn ] = isr_lpuart2, /* LPUART2 status/error interrupt */
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#endif
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#ifdef LPUART3
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[LPUART3_IRQn ] = isr_lpuart3, /* LPUART3 status/error interrupt */
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#endif
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#ifdef LPUART4
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[LPUART4_IRQn ] = isr_lpuart4, /* LPUART4 status/error interrupt */
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#endif
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#ifdef LPUART5
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[LPUART5_IRQn ] = isr_lpuart5, /* LPUART5 status/error interrupt */
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#endif
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#ifdef TSI0
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[TSI0_IRQn ] = isr_tsi0, /* TSI0 interrupt */
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#endif
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#ifdef TPM0
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[TPM0_IRQn ] = isr_tpm0, /* TPM1 fault, overflow and channels interrupt */
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#endif
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#ifdef TPM1
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[TPM1_IRQn ] = isr_tpm1, /* TPM1 fault, overflow and channels interrupt */
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#endif
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#ifdef TPM2
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[TPM2_IRQn ] = isr_tpm2, /* TPM2 fault, overflow and channels interrupt */
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#endif
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#ifdef USBHSDCD
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[USBHSDCD_IRQn ] = isr_usbhsdcd, /* USBHSDCD, USBHS Phy Interrupt */
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#endif
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#ifdef USBHS
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[USBHS_IRQn ] = isr_usbhs, /* USB high speed OTG interrupt */
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#endif
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#ifdef BTLE_RF
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[Radio_0_IRQn ] = isr_radio_0, /* Radio INT0 interrupt */
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#endif
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#ifdef ZLL
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[Radio_1_IRQn ] = isr_radio_1, /* Radio INT1 interrupt */
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#endif
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};
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/** @} */
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