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https://github.com/RIOT-OS/RIOT.git
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94 lines
3.5 KiB
C
94 lines
3.5 KiB
C
/*
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp32
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* @ingroup drivers_periph_gpio
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* @{
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*
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* @file
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* @brief Architecture-specific GPIO definitions for ESP32-C3 variant (family)
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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* @}
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*/
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#include "gpio_arch.h"
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#include "soc/io_mux_reg.h"
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#if !IS_USED(MODULE_ESP_IDF_GPIO_HAL)
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/* GPIO to IOMUX register mapping (see Technical Reference, Section 5.13.2 Register Summary)
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https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf */
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const uint32_t _gpio_to_iomux_reg[GPIO_PIN_NUMOF] =
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{
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PERIPHS_IO_MUX_XTAL_32K_P_U, /* GPIO0 used for XTAL_32K_P */
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PERIPHS_IO_MUX_XTAL_32K_N_U, /* GPIO1 used for XTAL_32K_N*/
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PERIPHS_IO_MUX_GPIO2_U, /* GPIO2 */
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PERIPHS_IO_MUX_GPIO3_U, /* GPIO3 */
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PERIPHS_IO_MUX_MTMS_U, /* GPIO4 */
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PERIPHS_IO_MUX_MTDI_U, /* GPIO5 */
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PERIPHS_IO_MUX_MTCK_U, /* GPIO6 */
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PERIPHS_IO_MUX_MTDO_U, /* GPIO7 */
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PERIPHS_IO_MUX_GPIO8_U, /* GPIO8 */
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PERIPHS_IO_MUX_GPIO9_U, /* GPIO9 */
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PERIPHS_IO_MUX_GPIO10_U, /* GPIO10 */
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PERIPHS_IO_MUX_VDD_SPI_U, /* GPIO11 */
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PERIPHS_IO_MUX_SPIHD_U, /* GPIO12 */
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PERIPHS_IO_MUX_SPIWP_U, /* GPIO13 */
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PERIPHS_IO_MUX_SPICS0_U, /* GPIO14 */
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PERIPHS_IO_MUX_SPICLK_U, /* GPIO15 */
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PERIPHS_IO_MUX_SPID_U, /* GPIO16 */
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PERIPHS_IO_MUX_SPIQ_U, /* GPIO17 */
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PERIPHS_IO_MUX_GPIO18_U, /* GPIO18 */
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PERIPHS_IO_MUX_GPIO19_U, /* GPIO19 */
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PERIPHS_IO_MUX_U0RXD_U, /* GPIO20 */
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PERIPHS_IO_MUX_U0TXD_U, /* GPIO21 */
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};
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#endif /* !IS_USED(MODULE_ESP_IDF_GPIO_HAL) */
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/* Table of the usage type of each GPIO pin */
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gpio_pin_usage_t _gpio_pin_usage[GPIO_PIN_NUMOF] = {
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#if MODULE_ESP_RTC_TIMER_32K
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_NOT_EXIST, /* GPIO0 is used for external 32K crystal */
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_NOT_EXIST, /* GPIO1 is used for external 32K crystal */
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#else
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_GPIO, /* GPIO0 */
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_GPIO, /* GPIO1 */
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#endif
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_GPIO, /* GPIO2 */
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_GPIO, /* GPIO3 */
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_GPIO, /* GPIO4 */
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_GPIO, /* GPIO5 */
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_GPIO, /* GPIO6 */
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_GPIO, /* GPIO7 */
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_GPIO, /* GPIO8 */
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_GPIO, /* GPIO9 */
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_GPIO, /* GPIO10 */
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_NOT_EXIST, /* GPIO11 is used as SPI VDD */
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#if defined(CONFIG_FLASHMODE_QIO) || defined(CONFIG_FLASHMODE_QOUT)
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/* in qio and qout mode these pins are used for Flash */
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_SPIF, /* GPIO12 is used as direct I/O SPI HD for Flash */
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_SPIF, /* GPIO13 is used as direct I/O SPI WP for Flash */
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#else
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/* otherwise these pins can be used as GPIO */
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_GPIO, /* GPIO12 */
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_GPIO, /* GPIO13 */
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#endif
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_SPIF, /* GPIO14 is used as direct I/O SPI CS0 for Flash */
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_SPIF, /* GPIO15 is used as direct I/O SPI CLK for Flash */
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_SPIF, /* GPIO16 is used as direct I/O SPI MISO for Flash */
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_SPIF, /* GPIO17 is used as direct I/O SPI MOSI for Flash */
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_GPIO, /* GPIO18 could be used for builtin USB2JTAG bridge */
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_GPIO, /* GPIO19 could be used for builtin USB2JTAG bridge */
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_UART, /* GPIO20 is used as direct I/O UART0 RxD */
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_UART, /* GPIO21 is used as direct I/O UART0 TxD */
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};
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